Award Abstract # 9730919
Hierarchical Testability Analysis and Design Verification for Analog and Mixed-Signal Systems

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF WASHINGTON
Initial Amendment Date: July 7, 1998
Latest Amendment Date: July 7, 1998
Award Number: 9730919
Award Instrument: Standard Grant
Program Manager: John Cozzens
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: July 15, 1998
End Date: June 30, 2001 (Estimated)
Total Intended Award Amount: $130,000.00
Total Awarded Amount to Date: $130,000.00
Funds Obligated to Date: FY 1998 = $130,000.00
History of Investigator:
  • Mani Soma (Principal Investigator)
    manisoma@u.washington.edu
Recipient Sponsored Research Office: University of Washington
4333 BROOKLYN AVE NE
SEATTLE
WA  US  98195-1016
(206)543-4043
Sponsor Congressional District: 07
Primary Place of Performance: University of Washington
4333 BROOKLYN AVE NE
SEATTLE
WA  US  98195-1016
Primary Place of Performance
Congressional District:
07
Unique Entity Identifier (UEI): HD1WMN6945W6
Parent UEI:
NSF Program(s): DES AUTO FOR MICRO & NANO SYS
Primary Program Source: app-0198 
Program Reference Code(s): 9148, 9215, MANU
Program Element Code(s): 471000
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This joint work between Prof. Mani Soma (U. of Washington) and Jacob Abraham (U. of Texas). The research is on fault models, test generation, and design verification for analog and mixed-signal Integrated circuits. A top-down approach to test and verification in mixed-signal design is being pursued. Research topics include the following. Develop algorithms for abstracting a circuit from the description of a mixed-signal circuit. Define testability figures of merit for major analog blocks such as converters, filters, etc., and develop methods to compute them. Investigate algorithms to evaluate testability of mixed-signal design using high level design information. For design verification, the group is finding accurate transformation algorithms to map analog blocks to discretized form. Also, abstractions to reduce state space complexity during verification are being explored. The algorithms and methods are being built into testability and test tools.

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