ABSTRACT

Future wireless systems such as those proposed for the sixth generation of wireless networks (6G) will expand upon our present networking capability and provide for new and emerging services such as augmented/virtual reality, remote surgery, sensing, and imaging of our environment. This will require new wireless circuits and systems that are more precise than those required for previous generations of wireless networks. The goal of this research is to use machine learning to continuously improve the precision and accuracy of wireless circuits and systems. This can enable wireless devices to operate more efficiently and provide more robust wireless connectivity. The proposed investigation will also provide insight into embedding machine learning directly with RF transceiver hardware. This research that is focused on the investigation of CHIPS will result in the design of novel integrated circuit and integration techniques that are promising for 6G. In addition to the scientific outcomes of the investigation, this proposal involves international collaboration between universities in the United States and Taiwan. The educational objectives will cross-train 4 Ph. D. and 4 M.S. students between the partnering universities in both countries. The investigators also plan curriculum development for their undergraduate and graduate courses in circuits and systems design and plan to involve undergraduate students from their courses at earlier stages of their educational development in the research associated with the proposal.

The objective of this proposal is to investigate the use of machine learning to continuously calibrate and optimize millimeter wave (mmWave) transceiver hardware. This is warranted because the projections for 6G expand the use of mmWave and near-THz spectrum, which require circuits and systems that can operate flexibly and with better linearity across wider instantaneous bandwidth. Commercially produced transceivers now use 100s-1000s of bits for trimming and calibration; however, many of these trims are only performed at the initial programming of the integrated circuit on automated testing equipment. This creates a large calibration and optimization space that this project will use to investigate continuous background optimizations using a local, efficient neuromorphic compute-in-memory system. As part of the program, highly trimmable digital transmitters will be integrated with a low-power calibration receiver that will be used to estimate transmitter parameters. The outputs of the receiver will be input into a neuromorphic computing accelerator with compute-in-memory (CIM) that will be running calibration/optimization algorithms that control the transmitters trimming and calibration bits. The project has two phases. In the first phase, the transceiver circuits and neuromorphic computing accelerator will be designed separately and characterized. They will be co-packaged for initial investigation of the interface between the systems. In the second phase, the experimental findings from phase one will be used to guide integration in phase two. The phase two demonstration experiment includes a fully integrated system and experiments on system optimizations to improve the system efficiency and linearity. The findings from these experiments will provide relevant information to scale designs for future systems that add complexity including multiple-input, multiple-output systems for wireless beamforming.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

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