The goal of this project is to explore a novel self-predictive and self-adaptive cybermanufacturing of semiconductor devices through die- or device-based (instead of wafer-based) adaptations in each process step guided by a predictive computation framework. In this semiconductor cybermanufacturing, device-to-device adaptions in geometrics and designs are applied in each process step to intelligently compensate for the variability in inherent material properties and historical process steps. A physical simulation augmented machine learning (ML) framework is proposed to enable this cybermanufacturing. This new manufacturing paradigm is expected to allow for transformative improvement in semiconductor manufacturing yield, particularly for emerging semiconductor and device technologies. The objective of this project is to identify and address the relevant fundamental knowledge gaps, using the small-scale fabrication of vertical gallium nitride (GaN) power diodes as a demonstration vehicle, which is an emerging wide-bandgap device for power applications in electric vehicle, power grid, and renewable energy processing. This project also aims at training the future workforce with a comprehensive skillset of semiconductor manufacturing and machine learning. This project builds on a collaboration between Virginia Tech and San Jose State University (SJSU).

In the first year of the project, an edge termination – the key building block in power devices to enable near-ideal breakdown voltage (BV) – has been developed for GaN devices, i.e., a guard ring (GR) edge termination formed by selective-area nitrogen implantation through an epitaxial p-GaN layer. The fabrication of this termination only includes a single implantation step that does not require precise control of implant depth, rendering a large process latitude. The number and spacing of guard ring are found to determine the BV. The 16-ring structure enables a BV of 1800 V, being 88% of the theoretical 1-D parallel-plane limit. Avalanche characteristics are observed in devices with a large variety of GR designs. The high efficiency (among the highest reported in avalanche-capable GaN terminations), simple and robust fabrication process, and uniform avalanche capability make this implanted GR a promising edge termination for high-voltage GaN devices.

In the second and third year, a cybermanufacturing framework has been successfully constructed and experimentally demonstrated. The framework is formed by an optimizer with a neural network (NN) as its surrogate model. The NN is trained by technology computer-aided design (TCAD) simulation data which is verified and calibrated to experimental data. Fabrication of GaN p-n diode with guard rings on 100 mm wafers is used for experimental demonstration. TCAD simulation is calibrated to experimental data to accurately predict the BV of GaN diodes with various numbers of guard rings of different widths and spacings. The calibration was performed carefully without overfitting and thus it can predict the BV of another set of unseen experiments with an accuracy of ±15%. It can also correctly predict the peak and trend of BV as a function of guard ring spacing in the unseen experiment. Afterward, the framework takes the guard ring spacing variations from the previous fabrication step as inputs and predicts the BV degradation using the NN. Through the optimizer, it then designs additional guard rings with the right number, spacing, and width for the next manufacturing step to compensate for the BV degradation due to the previous process variation. Its prediction is experimentally verified to be able to improve the manufacturing yield. From the comparison of two wafers, one based on conventional manufacturing and the other based on cybermanufacturing, the histogram of device BV from over 100 dies shows a mean value increase from 700 V to 800 V, resulting in the improvement of BV yield from 45% to 94% (based on the criterion BV > 700 V, i.e., >70% of the theoretical limit).

The above research has produced 6 publications in peer-reviewed journals and conference proceedings. Three master’s students and 3 undergraduate students were trained in TCAD and machine learning in the last 3 years. One PhD student was trained in device design and wafer-scale fabrication. Two summer classes were offered to high school students on machine learning.

Last Modified: 02/17/2025
Modified by: Hiu Yung Wong