The objective of this project is to develop advanced EM-aware physical optimization techniques and run-time circuit-level EM mitigation techniques for traditional 2D and 3D stacked ICs in nanometer regime. Following are major tasks finished:

1. EM-aware and EM-lifetime constrained power grid optimization considering multi-segment interconnect wires
2. Dynamic reliability management for multi-core processor based on deep reinforcement Learning
3. Long-term reliability management for multitasking GPGPUs
4. Reliability based hardware trojan design based on physics-based electromigration models
5. EMSpice: physics-based electromigration check using coupled electronic and stress simulation
6. Reliable power grid network design framework considering EM immortalities for multi-segment wires 
7. An adaptive electromigration assessment algorithm for full-chip power/ground networks
8. A fast semi-analytic approach for combined electromigration and thermomigration analysis for general multi-segment interconnects
9. Run-time accuracy reconfigurable stochastic computing for dynamic reliability and power management 
10. Data-driven fast stress analysis for multi-segment interconnects
11. Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks
12. Electromigration immortality check considering Joule heating effect of multi-segment wires
13. Fast electrostatic analysis for VLSI aging based on generative learning 
14. Fast electromigration stress analysis considering spatial Joule heating effects
15. Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks

In the following, we list the three major contributions from this award:

In the following, we list the three major contributions from this award:

(1)  EMSpice: physics-based electromigration check using coupled electronic and stress simulation

In this work, we proposed a novel full-chip EM simulation  tool, called EMSpice simulator. The new method starts from first principles and simultaneously considers two major interplaying physics effects in EM failure process: the hydrostatic  stress and electronic current/voltage in a power grid network. It then removes immortal interconnect wires by considering both   nucleation phase immortality and incubation phase immortality for   multi-segment interconnects.  Experimental results on two practical processor chip designs show  that the proposed coupled EM-IR drop analysis method can further  reduce the overly conservative EM-aware power grid design as the  number of the failed trees found by  EMSpice simulator is up to  76.7% less than the Black's method and 66.7% less than a recently  proposed full-chip EM analysis method  respectively. [Sun, TDMR’20]

(2)  Run-time accuracy reconfigurable stochastic computing for dynamic reliability and power management 

In this work, we propose a novel accuracy-reconfigurable stochastic  computing (ARSC) framework for dynamic reliability and power  management. Different than the existing stochastic computing works,  where the accuracy versus power/energy trade-off is carried out in.   the design time, the new ARSC design can change accuracy or  bit-width of the data in the run-time so that it can accommodate the  long-term aging effects by slowing the system clock frequency at  the cost of accuracy while maintaining the throughput of the  computing. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques. This technique is also demonstrated o the deep neural networks. Experimental results show that new ARSC DNN can sufficiently compensate  the NBTI induced aging effects in 10 years with marginal classification   accuracy loss while maintaining or even exceeding the pre-aging computing  throughput. [Yu, CASES’20, Liu, ISQED’21]

(3)  Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks

In this work, we proposed a fast full-chip electromigration (EM) aware IR drop constrained optimization framework, named {\it GridNetOpt}, for on-chip power grid networks accelerated by deep neural networks (DNN). Compared to the existing linear programming-based methods, the new method employs more flexible conjugate gradient-based optimization to size the wire width of the power grids. To mitigate the high cost of sensitivity calculation of the adjoint network using full-chip IR drop analysis at every iteration step, the sensitivity is computed via a trained conditional generative adversarial network (CGAN). Numerical results on a number of synthesized power grid benchmarks from ARM Cortex-M0 processor designs show that the proposed GridNetOpt can lead to at least an order of magnitude speedup over the conjugate gradient-based method using the traditional adjoint network method. [Zhou, ICCAD’20, Zhou, TCAD’21]

 The PI's team has published 15 conference papers and 13 journal papers, one book, one book chapter.  On the education side, five Ph.D. students who participated this project and received supports from this award, graduated from UCR including  Dr. Zeyu Sun, Dr. Chase Cook, Dr. Han Zhou, Dr. Shaoyi Peng and and Dr. Sheriff Sadiqbatcha. All the Ph.D. students joined the US companies such as Intel Corporation, Cadence Design System, Synopsys Corporation etc.

 In addition, several undergraduate student researchers, such as Karina Rowe (female, Latino), Winson Bi, Carson Welty, Cole Pivonka, Cindy Ho (female), Michael O?dea, Jonathan Clarke, Ally Thach (female) , Christian Campos (Latino), who were supported by REU funds of this award and other programs. They worked on various projects related to this project. 

Last Modified: 01/29/2023
Modified by: Sheldon X Tan