| NSF Org: |
CNS Division Of Computer and Network Systems |
| Recipient: |
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| Initial Amendment Date: | July 20, 2018 |
| Latest Amendment Date: | July 20, 2018 |
| Award Number: | 1812600 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Karen Karavanic
kkaravan@nsf.gov (703)292-2594 CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | August 1, 2018 |
| End Date: | July 31, 2023 (Estimated) |
| Total Intended Award Amount: | $312,210.00 |
| Total Awarded Amount to Date: | $312,210.00 |
| Funds Obligated to Date: |
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| History of Investigator: |
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| Recipient Sponsored Research Office: |
21 N PARK ST STE 6301 MADISON WI US 53715-1218 (608)262-3822 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
21 North Park Street Suite 6401 Madison WI US 53715-1218 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): | Secure &Trustworthy Cyberspace |
| Primary Program Source: |
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| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Integrated circuit fabrication has spread across the globe, with over 90% of the world's fabrication capacity controlled by non-US companies. This project is on studying the security of chip fabrication by an untrusted foundry. The fabrication technique, known as split manufacturing, is based on partial sharing of the chip design information with the untrusted foundry in order to protect the intellectual property of the chip. With this technique, only a challenging portion of the chip is manufactured at the untrusted foundry. The remaining is completed by a trusted and smaller-scale foundry.
Specific research tasks include: (a) use of machine learning techniques to decide an appropriate "split level" to divide the chip design files into trusted and untrusted portions; (b) developing design-aid tools to obfuscate the chip layout files in order to make reverse engineering by the untrusted foundry infeasible; (c) development and public release of a software tool to generate various split-manufactured instances from the design files of the full chip, in order to promote research in this area.
Besides the release of the software tool, research findings will be published across communities related to the fields of hardware security and Integrated Circuit design. Specific components of the project are designed to promote involvement of undergraduate students in research. Involvement of women and underrepresented students in research will be pursued at all levels.
Data and software tools will be publicly accessible from http://homepages.cae.wisc.edu/~adavoodi/split-man.htm and will remain active for at least two years following the end date of the award.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
Manufacturing outsourcing of Integrated Circuits has become more common than ever before because of the high cost of fabricating high-end chips. As a result, security issues including design piracy and hardware Trojans injection may arise when an untrusted foundry is involved in manufacturing. To alleviate these problems, split manufacturing has been proposed as a technique where the untrusted foundry only receives and fabricates a partial layout up to a metal layer denoted by a “split level”. This portion of the layout is referred to as the public portion. The remainder of the design includes the private layers and will be fabricated at a secondary stage by a trusted foundry.
This project first developed a machine learning (ML) attack model to show that an attacker may still guess the connectivity implied by the private layers using only the public layers. The ML attack model was shown to be significantly more effective compared to other existing attack models for this problem.
Next, this research developed a novel way to build a IC layout obfuscator for split manufacturing, based on recent advancements in the area of ``explainability'' of machine learning. The PIs adopted an explanatory metric, namely the SHapley Additive exPlanation (SHAP), to analyze the ML attack model developed earlier. The SHAP-based analysis reveals to what extent each layout feature contributes to correctly predicting each individual unknown connection as seen by an untrusted foundry. Next, this information is exploited to design a SHAP-guided obfuscator against the ML attack model where only truly vulnerable connections are identified and each is obfuscated by just the necessary amount, in order to minimize perturbations to the original design.
The source codes of the attack model and layout obfuscator were released on the "CAD for Assurance" repository for free download. The NSF award allowed partial support of two PhD students including one female student. Some of the conference and journal publications related to this award included collaborator from IBM as co-author.
Last Modified: 12/13/2023
Modified by: Azadeh Davoodi
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