Primary goals of this NSF research project were to analyze the major hardware security issues related to third-party intellectual property blocks (3PIPs), which are increasingly used in modern system on chip (SoC) designs and then investigate an integrative approach to trust verification of these IP blocks. Modern SoC designs involve integration of a large number of IP blocks, many of which are acquired from untrusted third-party vendors. This project greatly enhances our understanding of the related threat space, trust metrics to quantify level of assurance, and effective solutions for trust verification or trusted system operation with untrusted IP blocks.

The major intellectual contributions of the project are described next in detail.

The need to secure hardware devices in the untrusted supply chain ecosystem has instigated a wide body of research. However, newer attacks are developed that are capable of bypassing the known methods, thus creating an arms race commonly observed in software security research. Detection of malicious circuits in broader categories of microelectronic components and emerging technologies provide an interesting avenue for future research. We have explored combination of design for test (DFT) and trust verification solutions could be explored to combat these new challenges.

Quantifying the degree to which a device can be trusted is also challenging problem. We have developed a suite of trust metrics that quantify the presence of a specific vulnerability in the hardware or the coverage of a solution against a particular vulnerability. Logic testing based Trojan detection methods can benefit from trigger coverage and Trojan coverage metric to represent the ability of generated test patterns in triggering and detecting a large number of hard-to-activate Trojans. Hardware Trojans are likely to be formed utilizing the rarely switching nets of the design. Even when they are triggered, their malicious impact may not be observable at the output. Test vectors with high trigger coverage are expected to switch those nets to their rare values; thus, increasing the probability of triggering potential Trojans.

We have developed novel countermeasures that apply to COTS-based manufacturing processes used in consumer, commercial and military products is an interesting avenue for exploration. Trust verification of COTS components using logic testing would require efficient test generation using only high-level specification of the suspect component. Application of side-channel analysis (SCA) based verification has been studied as well by leveraging self-referencing techniques that can utilize the side-channel signature of an untrusted component as a reference.

An IP containing a security vulnerability—whether inadvertent or malicious—may compromise the trustworthiness of the entire SoC, e.g., by leaking sensitive information or causing execution failures at key points. Existing functional validation approaches, post-manufacturing tests, and IP trust verification techniques are inadequate to accomplish comprehensive system-level security assurance in the presence of untrusted IPs. In this work, we have also analyzed the security issues at the SoC level caused by untrusted IPs. We have developed a novel, resilient SoC security architecture to ensure trusted SoC operation with untrusted IPs. Our architecture realizes fine-grained IP-trust aware security policies in an efficient security policy checker that enables runtime monitoring of security issues arising from untrusted IPs. We have demonstrated the effectiveness of this framework for system protection using several illustrative practical use cases. 

Outreach

We have pursued diverse outreach activities in this project. Besides publishing and presenting technical articles, organizing special sessions or tutorials in conferences, guest-editing special issues in journal, we have also developed the CAD for Assurance Website, supported by the Hardware Security Community: https://cadforassurance.org/

The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with an easy-to-search and easy-to-access interface. We’ve included information on many major CAD tools the research community have developed over the past decade, including open-source license-free or ready-for-licensing tools, associated metrics, relevant publications and video-demos.

Future Directions:

The research findings and educational efforts undertaken in this project are expected to create pathways for many future explorations and development.

(1) Exploration of new attack modalities and further enhancing the threat space for third-party IP blocks of various types, including analog and mixed-signal IP blocks, which this project  

(2)   Future work on hardware IP protection will involve extension of the functional and machine learning based trust verification of large intellectual property blocks and SoCs and development of new metrics and evaluation on industrial designs.

(3)   Future work on hardware Trojan detection will involve application of advanced statistical analysis as well as machine learning techniques to improve the detection accuracy and the confidence level.

Last Modified: 02/03/2021
Modified by: Swarup K Bhunia