Award Abstract # 1528181
CCF: SHF: Small: Collaborative Research: Domain-specific Reconfigurable Processor for Time-Series Data Mining and Monitoring

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: REGENTS OF THE UNIVERSITY OF CALIFORNIA AT RIVERSIDE
Initial Amendment Date: September 1, 2015
Latest Amendment Date: June 16, 2020
Award Number: 1528181
Award Instrument: Standard Grant
Program Manager: Yuanyuan Yang
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: September 1, 2015
End Date: August 31, 2021 (Estimated)
Total Intended Award Amount: $262,206.00
Total Awarded Amount to Date: $343,247.00
Funds Obligated to Date: FY 2015 = $262,206.00
FY 2016 = $49,041.00

FY 2018 = $16,000.00

FY 2020 = $16,000.00
History of Investigator:
  • Philip Brisk (Principal Investigator)
    philip@cs.ucr.edu
Recipient Sponsored Research Office: University of California-Riverside
200 UNIVERSTY OFC BUILDING
RIVERSIDE
CA  US  92521-0001
(951)827-5535
Sponsor Congressional District: 39
Primary Place of Performance: University of California-Riverside
900 University Avenue
Riverside
CA  US  92521-0001
Primary Place of Performance
Congressional District:
39
Unique Entity Identifier (UEI): MR5QC5FCAVH5
Parent UEI:
NSF Program(s): Special Projects - CCF,
Software & Hardware Foundation
Primary Program Source: 01001516DB NSF RESEARCH & RELATED ACTIVIT
01001617DB NSF RESEARCH & RELATED ACTIVIT

01001819DB NSF RESEARCH & RELATED ACTIVIT

01002021DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 7923, 7941, 8091, 9251
Program Element Code(s): 287800, 779800
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This proposal will investigate techniques to improve performance and reduce the cost and energy consumption of wearable devices (e.g., Internet-of-Things) that perform real-time medical monitoring. The objective is to demonstrate how to construct programmable integrated circuits that can provide monitoring capabilities while remaining small enough to be convenient and unobtrusive to the wearer. As a motivating example, such a device could detect and predict medical problems of fundamental importance such as pericardial tamponade, a life-threatening emergency where in the pericardium (a sac surrounding the heart) fills with fluid and prevents the heart from pumping blood, leading quickly and directly to death. Broader impacts of this effort include: reducing the cost of medical monitoring and saving lives; introduction of undergraduate students at both institutions to hardware/software co-design for wearable computing through a Freshman Discovery Seminar; inclusion of women and underrepresented minorities in the project; public release of hardware and software developed in the course of this project; and tutorial dissemination targeting the database/data mining and design automation research communities.


The technical approach will involve the creation of application-specific integrated circuit hardware that can be added to embedded processors and microcontrollers to improve the performance of real-time medical monitoring applications. The research is based on the observation that real world data sets often exhibit a significant disparity in the dimensionality (data sampling rate) and cardinality (number of distinct values) of the data; for example, echocardiograms (ECGs) are often sampled at 1,024 Hz and 64-bits, although reducing the dimensionality to 128 Hz and the cardinality to 8-bits suffice for real-time monitoring. The fundamental challenge is that the minimum dimensionality and cardinality may vary from task-to-task, from individual-to-individual, and possibly even from hour-to-hour for a given individual. The Minimum Description Length (MDL) principle will be investigated as a potential solution to find the intrinsic dimensionality and cardinality of the data source, which can reduce data volume and improve detection accuracy by noise reduction. This information will then be leveraged to design domain-specific adaptive architectures that can exploit this reduced data volume to improve throughput and enhance battery lifetime.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

Note:  When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

(Showing: 1 - 10 of 19)
Abdullah Mueen, Nikan Chavoshi, Noor Abu-El-Rub, Hossein Hamooni, and Amanda Minnich "Fast Warping Distance for Sparse Time Series" IEEE ICDM , 2016
Amin Kalantar, Zachary Zimmerman, Philip Brisk "FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction" Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , 2021 , p.40 10.1109/FCCM51124.2021.00013
Chin-Chia Michael Yeh, Yan Zhu, Liudmila Ulanova, Nurjahan Begum, Yifei Ding, Hoang Anh Dau, Diego Silva, Abdullah Mueen, and Eamonn Keogh "All Pairs Similarity Joins for Time Series Subsequences" IEEE ICDM , 2016
Gener, Serhan and Newton, Parker and Tan, Daniel and Richelson, Silas and Lemieux, Guy and Brisk, Philip "An FPGA-based Programmable Vector Engine for Fast Fully Homomorphic Encryption over the Torus" SPSL: Secure and Private Systems for Machine Learning (ISCA Workshop) , 2021 Citation Details
Kalantar, Amin and Zimmerman, Zachary and Brisk, Philip "FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction" International Symposium on Field-Programmable Custom Computing Machines , 2021 https://doi.org/10.1109/FCCM51124.2021.00013 Citation Details
Kenneth O'Neal and Philip Brisk "Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey" 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2018 , p.763 10.1109/ISVLSI.2018.00143
Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard and Philip Brisk "HLSPredict: cross platform performance prediction for FPGA high-Level synthesis" International Conference on Computer-Aided Design (ICCAD) , 2018
Kenneth O'Neal, Philip Brisk, Emily Shriver, and Michael Kishinevsky "HALWPE Hardware-Assisted Light Weight Performance Estimation for GPUs" Design Automation Conference (DAC) , 2017 , p.article # 10.1145/3061639.3062257
Kenneth O'Neal, Philip Brisk, Emily Shriver, and Michael Kishinevsky "Hardware-Assisted Cross-Generation Prediction of GPUs Under Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , 2019 10.1109/TCAD.2018.2834398
Kenneth O'Neal, Philip Brisk, Zack Waters, Ahmed Abousamra and Emily Shriver "GPU Performance Estimation Using software Rasterization and Machine Learning" ACM Transactions on Embedded Computing Systems (TECS) , v.16 , 2017 10.1145/3126557
Maryam Shahcheraghi, Trevor Cappon, Samet Oymak, Vagelis Papalexakis, Eamonn Keogh, Zachary Zimmerman, and Philip Brisk "Matrix Profile Index Prediction for Streaming Time Series" ML for Systems Workshop @ NeurIPS 2020 , 2021
(Showing: 1 - 10 of 19)

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

This project investigated computing algorithm-hardware-software codesign for time series data mining algorithms. The objective was to develop high-performance and power-efficient custom computing solutions for cutting-edge algorithms that can rapidly process data obtained from Internet-of-Things (IoT) sensors. As the project evolved, the needs and capabilities for real-time data processing at the edge and more powerful offline data processing within the cloud rapidly diverged. The PI and his team were able to successfully investigate accelerated computing solutions in both domains, yielding solutions that are usable both by academic researchers and industrial practitioners. 

The intellectual Merit of the project's research activities focus on the Matrix Profile, a data structure and collection of associated algorithms that can identify and efficiently represent both repeated patterns and anomalies in time series. The Matrix Profile is robust, scalable, and largely parameter-free. As originally defined, the Matrix Profile assumes that the entire time series has been measured and stored offline for processing later. This project included the development of a number of algorithms to compute the Matrix Profile as efficiently as possible. The most successful of these algorithms is called SCAlable Matrix Profile (SCAMP), and can be deployed on CPUs and/or GPUs at the data center scale. SCAMP is the fastest Matrix Profile code available to date, and has been publicly released on GitHub:

https://github.com/zpzim/SCAMP

One key limitation of SCAMP is that it cannot efficiently handle streaming data that may be produced, for example, using IoT sensors. To address the case of streaming data, the PI and team investigated machine learning techniques, leading to the Learned Approximate Matrix Profile (LAMP), which efficiently predicts (rather than directly computing) the Matrix Profile. LAMP can be deployed on low-cost embedded systems (e.g., Raspberry Pi), while achieving inference rates high-enough to process data in real-time. Source code for LAMP has been publicly released on GitHub:

https://github.com/zpzim/LAMP-ICDM2019

LAMP can achieve higher inference rates using hardware acceleration. The PI and team successfully ported LAMP to Xilinx Field Programmable Gate Arrays (FPGAs) using the Vitis Unified Software Platform, achieving significantly higher inference rates. Initially, the project targeted a low-cost consumer-grade FPGA, the Ultra96-v2 platform, and eventually migrated to a much larger-capacity part, the Alveo U250. Source code for FPGA-accelerated LAMP has been publicly released on GitHub:

https://github.com/aminiok1/LAMP-FPGA

and

https://github.com/aminiok1/fccm-lamp

SCAMP and LAMP have been evaluated on a number of datasets relevant to scientists, from diverse domains including seismology, entomology (insect penetration graphs), and zoology (a Fitbit-like device worn by chickens) and neuroscience (neural cell cultures). This project has also investigated relationships between performance counters that are integrated into modern computing hardware (CPUs, GPUs, etc.) and their utility in terms of predicting performance and power consumption of applications, as they are ported from one platform to another. 

The Broader Impacts of this project include: benefits to society from the ability to process data obtained from IoT sensors in real-time; there has been a specific emphasis on the study of seismology data, which has enabled unprecedented success in terms of identifying seismic events that were not previously reported in earthquake catalogs, as well as low frequency earthquakes whose underlying mechanisms are not fully understood.

This project has also trained several graduate students, and one postdoc, and provided research experience for a number of undergraduate students, including women and minorities who have been historically represented in the sciences; multiple undergraduate students who participated in the project were able to successfully co-author papers with the PI that were published in top peer-reviewed conferences and journals. The PI participated in a series of biologically-themed Hack-a-thons organized by undergraduate students enrolled at UC Riverside, and presented research results from this project to UC Riverside student organizations.The PI also helped several of the students trained by this award train K12 teachers in Computer Science principles, leading the eventual conferal of California State supplemental authorization for Computer Science Education.

Several project stakeholderscreated the Matrix Profile foundation, whose goal is to facilitate community awareness and adoption of the Matrix Profile and its releated algorithm; see:

https://www.matrixprofile.org

and

https://ui.matrixprofile.org

for interactive resources and tutorials.

A number of companies, including Target Corporation and TD Ameritrade have adopted the Matrix Profile for their own internal use, and a researcher associated with TD Ameritrade created a Matrix Profile library called STUMPY, which has been released publicly.

Altogether, these outcomes indicate the the efforts of this project have been translated successfully to industry and software artifacts have been made publicly available to benefit the US Taxpayer. 


Last Modified: 11/06/2021
Modified by: Philip L Brisk

Please report errors in award information by writing to: awardsearch@nsf.gov.

Print this page

Back to Top of page