Award Abstract # 1453378
CAREER: Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: CORNELL UNIVERSITY
Initial Amendment Date: January 21, 2015
Latest Amendment Date: May 1, 2019
Award Number: 1453378
Award Instrument: Continuing Grant
Program Manager: Sankar Basu
sabasu@nsf.gov
 (703)292-7843
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: March 1, 2015
End Date: February 28, 2022 (Estimated)
Total Intended Award Amount: $453,036.00
Total Awarded Amount to Date: $453,036.00
Funds Obligated to Date: FY 2015 = $173,017.00
FY 2017 = $89,390.00

FY 2018 = $97,064.00

FY 2019 = $93,565.00
History of Investigator:
  • Zhiru Zhang (Principal Investigator)
    zhiruz@cornell.edu
Recipient Sponsored Research Office: Cornell University
341 PINE TREE RD
ITHACA
NY  US  14850-2820
(607)255-5014
Sponsor Congressional District: 19
Primary Place of Performance: Cornell University
320 Rhodes Hall
Ithaca
NY  US  14853-3801
Primary Place of Performance
Congressional District:
19
Unique Entity Identifier (UEI): G56PUALJ3KT5
Parent UEI:
NSF Program(s): Software & Hardware Foundation
Primary Program Source: 01001516DB NSF RESEARCH & RELATED ACTIVIT
01001718DB NSF RESEARCH & RELATED ACTIVIT

01001819DB NSF RESEARCH & RELATED ACTIVIT

01001920DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 1045, 7945
Program Element Code(s): 779800
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This CAREER research project aims to significantly improve the design productivity and quality of heterogeneous computer architectures, which extensively integrate specialized hardware accelerators to continue to provide the computing improvements essential to all aspects of our society. Achieving this goal requires the development of a new class of truly integrated design automation methodologies and tools to enable productive modeling, exploration, and generation of hardware accelerators from high-level programs, especially for the irregular programs that are commonplace in emerging application domains such as computer vision, machine learning, physical simulation, and social network analytics. The project also has a broad yet thematically focused plan for educational outreach, which aims to cultivate the next generation of engineers and scientists who can bridge the chasm between the software and hardware design paradigms. The PI will lead hands-on design sessions for underrepresented minority high school students and organize engineering seminars with engaging demonstrations for first-year undergraduates to increase their interest and participation in computer engineering. In addition, the PI will actively integrate the research outcomes into undergraduate and graduate curriculum development, and leverage industrial collaborations to effectively disseminate the research results on heterogeneous computing to a broader audience.


Diminished benefits of technology scaling have led to a growing interest in heterogeneous accelerator-rich system architectures to improve performance under tight power and energy efficiency constraints. Irregular programs are gaining prominence in many important application domains; but these programs are much more difficult to parallelize on conventional data-parallel accelerators such as GPUs, as they typically exhibit less-structured data access patterns and difficult-to-predict dynamic parallelism. This project aims to develop a synergistic design automation framework where a set of novel programming abstractions, architectural templates, synthesis optimization algorithms, and hardware prototypes all play concerted roles to overcome the many challenges raised by the irregular programs. Specifically, the key idea is to automatically generate softly synthesized accelerators that are capable of decoupling data access from computation for tolerating memory latency and performing run-time optimizations for exploiting the irregular parallelism.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 28)
Ritchie Zhao, Mingxing Tan, Steve Haihang Dai, Zhiru Zhang "Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis" 52nd Design Automation Conference (DAC-52) , 2015
Dai, Steve and Liu, Gai and Zhang, Zhiru "A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation" International Symposium on Field-Programmable Gate Arrays , 2018 10.1145/3174243.3174268 Citation Details
Dai, Steve and Zhang, Zhiru "Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning" The 56th Annual Design Automation Conference (DAC) , 2019 10.1145/3316781.3317842 Citation Details
Du, Yixiao and Hu, Yuwei and Zhou, Zhongchun and Zhang, Zhiru "High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV" ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , 2022 https://doi.org/10.1145/3490422.3502368 Citation Details
Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang "Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , v.36 , 2017 10.1109/TCAD.2017.2664067
Hua, Weizhe and Zhou, Yuan and De Sa, Christopher and Zhang, Zhiru and Suh, G. Edward "Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating" International Symposium on Microarchitecture (MICRO) , 2019 10.1145/3352460.3358283 Citation Details
Hu, Yuwei and Du, Yixiao and Ustun, Ecenur and Zhang, Zhiru "GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs" IEEE/ACM International Conference On Computer Aided Design (ICCAD) , 2021 https://doi.org/10.1109/ICCAD51958.2021.9643582 Citation Details
Lai, Yi-Hsiang and Chi, Yuze and Hu, Yuwei and Wang, Jie and Yu, Cody Hao and Zhou, Yuan and Cong, Jason and Zhang, Zhiru "HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing" FPGA 2019 , 2019 10.1145/3289602.3293910 Citation Details
Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Haihang Dai, Zhiru Zhang "ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests" 35th International Conference on Computer-Aided Design (ICCAD-35) , 2015
Nitish Srivastava, Hanchen Jin, Jie Liu, David Albonesi, Zhiru Zhang "MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product" 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO-53) , 2020 10.1109/MICRO50266.2020.00068
Nitish Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David Albonesi, Zhiru Zhang "Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations" 26th IEEE International Symposium on High-Performance Computer Architecture (HPCA-26) , 2020 10.1109/HPCA47549.2020.00062
(Showing: 1 - 10 of 28)

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

Diminished benefits of technology scaling have led to a growing interest in heterogeneous accelerator-rich system architectures to improve performance under tight power and energy efficiency constraints. In parallel, irregular programs are gaining prominence in many important application domains; however, these programs are much more difficult to parallelize on conventional data-parallel accelerators such as GPUs, as they typically exhibit less-structured data access patterns and difficult-to-predict dynamic parallelism. Overcoming the challenge of productively creating hardware accelerators for irregular programs will enable major advances in design automation for future heterogeneous computing with pervasive hardware specialization. 

Given this motivation, the project took a synergistic approach and explored novel programming abstractions, architectural templates, synthesis optimization algorithms, and FPGA prototypes, which all played concerted roles to overcome the many challenges raised by the irregular programs. More specifically the PI and his research team designed, implemented, and evaluated a variety of novel specialized accelerators capable of efficiently executing various irregular workloads such as sparse linear algebra and graph processing. The research team also invented and evaluated several novel high-level synthesis (HLS) algorithms to enable automatically generating softly synthesized accelerators that are capable of decoupling data access from computation for tolerating memory latency. These studies have resulted in close to 20 publications in top conferences and journals in EDA, computer architecture, and FPGA. were put into practice using several hardware prototypes. In addition, several of the tools and benchmarks developed in this project have been released as open-source software projects.

As part of this project's educational outreach plan, the PI developed a new course targeted towards advanced undergraduate and first-year graduate students. This course focuses on high-level digital design automation and teaches students the algorithms and optimization techniques involved in automatically transforming software-based descriptions of algorithms into hardware descriptions. The PI also led a week-long design experience for high-school students as part of the CATALYST Academy. The CATALYST Academy is organized by the Office of Diversity Programming in Engineering at Cornell University, which focuses on young men and women of diverse racial, socioeconomic, and geographic backgrounds. CATALYST scholars spend their mornings learning about the various fields within engineering, and spend their afternoons working on the design project.


Last Modified: 06/23/2022
Modified by: Zhiru Zhang

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