| NSF Org: |
CNS Division Of Computer and Network Systems |
| Recipient: |
|
| Initial Amendment Date: | August 18, 2014 |
| Latest Amendment Date: | May 18, 2015 |
| Award Number: | 1422401 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Nina Amla
namla@nsf.gov (703)292-7991 CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | September 1, 2014 |
| End Date: | August 31, 2019 (Estimated) |
| Total Intended Award Amount: | $501,851.00 |
| Total Awarded Amount to Date: | $517,851.00 |
| Funds Obligated to Date: |
FY 2015 = $16,000.00 |
| History of Investigator: |
|
| Recipient Sponsored Research Office: |
4400 VESTAL PKWY E BINGHAMTON NY US 13902 (607)777-6136 |
| Sponsor Congressional District: |
|
| Primary Place of Performance: |
NY US 13902-6000 |
| Primary Place of
Performance Congressional District: |
|
| Unique Entity Identifier (UEI): |
|
| Parent UEI: |
|
| NSF Program(s): |
Special Projects - CNS, Secure &Trustworthy Cyberspace |
| Primary Program Source: |
01001516DB NSF RESEARCH & RELATED ACTIVIT |
| Program Reference Code(s): |
|
| Program Element Code(s): |
|
| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
In cache-based side-channel attacks, an attacker with no special privileges or physical access can extract secrets from a victim process by observing its memory accesses through a shared cache. Such attacks have been demonstrated on a number of platforms, and represent a dangerous and open threat. This project explores side-channel attacks on the shared lower-level-caches (LLCs) in modern CPUs.
The investigators demonstrate the feasibility of these types of attacks, and explores defenses against these attacks and against colluding attacks at different levels of the cache hierarchy. The project develops security metrics for expressing side-channel vulnerability and correlates them to the ease of reconstructing the secret data from the leaked side-channel information. These new metrics and tools developed in this work will assist in rigorous evaluation of the security of systems with respect to these types of attacks.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Note:
When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external
site maintained by the publisher. Some full text articles may not yet be available without a
charge during the embargo (administrative interval).
Some links on this page may take you to non-federal websites. Their policies may differ from
this site.
PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
Intellectual Merit:
The focus of this project was on comprehensive investigations of covert channels, as well as side-channel attacks and defense mechanisms in modern microprocessors and memory systems. Undertaken investigations emcompassed cache memory hierarchies, branch prediction units, random number generators and graphics processing units. The project also addressed recently-emerged transient execution attacks, and attacks on shared execution resources in SMT processors.
Specific intellectual contributions include: 1) A new faster side-channel attack on the last-level cache (paper published in DAC'2016); 2) A defense from this and other cache attacks based on relaxing inclusion property for multi-level caches (paper published in DAC'2017); 3) A new covert channel through branch predictor unit and its mitigations (paper published in ACM TACO'2016); 4) A new covert channel through random number generator unit and mitigation techniques (paper published in CCS'2016); 5) A side-channel attack on branch prediction unit to bypass address-space layout randomization and its mitigations (paper published in MICRO'2016, this work served as one of the motivations for Spectre attacks); 6) A new covert channel through GPGPU (paper published in MICRO 2017); 7) A defense against transient execution attacks, such as Spectre and Meltdown (paper published in DAC'2019); 8) A new design of Simultaneously Multithreaded (SMT) processors that makes them immune to side-channel attacks on execution units without significantly impacting performance.
Some of these works have received additional recognition from the community. DAC 2016 and PACT 2019 papers were nominated for best paper awards in the respective conferences. The work on ASLR bypass published in MICRO'2016 was invited for a presentation at Top Picks in Hardware and Embedded Security Workshop held in conjunction with ICCAD 2018. This work was also cited as one of the motivations for the development of Spectre attacks.
Broader Impacts:
Project activities included the development of a new graduate-level Hardware Security course that was taught several times at UCR. Each iteration of the course was refined based on the most recent developments in the area of hardware and architectural support for systems security. Existing computer architecture courses were refined to include security topics. Several graduate and undergraduate students were supported and trained on the project. Three of the PhD students supported on this grant obtained tenure-track faculty positions at research universities in the US.
Last Modified: 10/23/2019
Modified by: Dmitry V Ponomarev
Please report errors in award information by writing to: awardsearch@nsf.gov.
