Award Abstract # 1337198
XPS: DSD: Collaborative Research: NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF PITTSBURGH - OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
Initial Amendment Date: September 6, 2013
Latest Amendment Date: September 6, 2013
Award Number: 1337198
Award Instrument: Standard Grant
Program Manager: Tao Li
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: September 15, 2013
End Date: June 30, 2017 (Estimated)
Total Intended Award Amount: $450,000.00
Total Awarded Amount to Date: $450,000.00
Funds Obligated to Date: FY 2013 = $260,981.00
History of Investigator:
  • Hai Li (Principal Investigator)
    hai.li@duke.edu
  • Yiran Chen (Co-Principal Investigator)
Recipient Sponsored Research Office: University of Pittsburgh
4200 FIFTH AVENUE
PITTSBURGH
PA  US  15260-0001
(412)624-7400
Sponsor Congressional District: 12
Primary Place of Performance: University of Pittsburgh
3700 O'Hara Street
Pittsburgh
PA  US  15261-0001
Primary Place of Performance
Congressional District:
12
Unique Entity Identifier (UEI): MKAGLD59JRL1
Parent UEI:
NSF Program(s): Exploiting Parallel&Scalabilty
Primary Program Source: 01001314DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s):
Program Element Code(s): 828300
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

The explosion of "big data" applications imposes severe challenges of data processing speed and scalability on traditional computer systems. The performance of traditional Von Neumann machines is greatly hindered by the increasing performance gap between CPU and memory, motivating the active research on new or alternative computing architectures. By imitating brain's naturally massive parallel architecture with closely coupled memory and computing as well as the unique analog domain operations, neuromorphic computing systems are anticipated to deliver superior speed for applications in image recognition and natural language understanding.

The objective of this research is to establish the fundamental framework and design methodology for NeoNexus -- the next-generation information processing system inspired by human neocortex. It integrates neuromorphic computing accelerators with conventional computing resources by leveraging large scale inference-based data processing and computing acceleration technique atop memristor crossbar arrays. The computation and data exchange will be carefully coordinated and supported by the innovative interconnect architecture, i.e., a hierarchical network-on-chip (NoC). The software-hardware co-design platform will be developed to address the various design challenges. The project will help computer architecture and high-performance computing communities to overcome the ever-increasing technical challenges of traditional architectures and accelerate the fusion between conventional computing technology and cognitive computing model. It will also promote the applications of artificial intelligence technology advances in modern computer architectures and motivate the inventions at both software and hardware levels. Undergraduate and graduate students involved in this research will be trained for the next-generation semiconductor industry workforce.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 12)
B. Liu. X. Liu, C. Liu, W. Wen, M. Mao, H. Li, and Y. Chen "Hardware Acceleration for Neuromorphic Computing: An Evolving View" Non-Volatile Memory Technology Symposium (NVMTS) , 2015 10.1109/NVMTS.2015.7457496
B. Yan, A. M. Mahmoud, J. J. Yang, Q. Wu, Y. Chen, and H. Li "A Neuromorphic ASIC Design Using 1-Selector-1-Memristor Crossbar" IEEE International Symposium on Circuits and Systems (ISCAS) , 2016
H. Jiang, W. Zhu, F. Luo, K. Bai, C. Liu, X. Zhang, J. J. Yang, Q. Xia, and H. Li "Cyclical Sensing Integrate-and-Fire Circuit for Memristor Array Based Neuromorphic Computing" IEEE International Symposium on Circuits and Systems (ISCAS) , 2016
M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose, and W. Linderman "Memristor Crossbar Based Neuromorphic Computing System: A Case Study" IEEE Transactions on Neural Network and Learning System (TNNLS) , v.25 , 2014 , p.1864 10.1109/TNNLS.2013.2296777
M. Hu, Y. Wang, W. Wen, Y. Wang, and H. Li "Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems" IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) , 2016 10.1109/JETCAS.2016.2547780
Q. Qiu, Z. Li, K. Ahmed, W. Liu, S.-F. Habib, H. Li, and M. Hu "A Neuromorphic Architecture for Con-text Aware Text Image Recognition" the Journal of Signal Processing Systems , 2015 10.1007/s11265-015-1067-4
S. Duan, Z. Dong, X. Hu, L. Wang, and H. Li "Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition" Neural Computing and Applications , v.2015 , 2015 , p.1 10.1007/s00521-015-1899-7
S. Li, X. Liu, M. Mao, H. Li and Y. Chen "Heterogeneous Systems with Reconfigurable Neuromorphic Computing Accelerators" IEEE International Symposium on Circuits and Systems (ISCAS) , 2016
Wu, Chunpeng and Cheng, Hsin-Pai and Li, Sicheng and Li, Hai Helen and Chen, Yiran "ApesNet: A Pixel-wise Efficient Segmentation Network: Invited Special Session Paper" the Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 16) , 2016 10.1145/2993452.2994306 Citation Details
W. Wen, C. Wu, Y. Wang K. Nixon, Q. Wu, M. Barnell, H. Li, and Y. Chen "A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip" Design Automation Conference (DAC) , 2016
Z. Dong, S. Duan, X. Hu, L. Wang, and H. Li "A Novel Memristive Multilayer Feedforward Small-World Neural Network with its Applications in PID Control" The Scientific World Journal , 2014 , p.394828 10.1155/2014/394828
(Showing: 1 - 10 of 12)

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