NSF Org:	CCF Division of Computing and Communication Foundations
Recipient:	NORTH DAKOTA STATE UNIVERSITY
Initial Amendment Date:	May 31, 2011
Latest Amendment Date:	May 31, 2011
Award Number:	1116022
Award Instrument:	Standard Grant
Program Manager:	Ahmed Louri CCF  Division of Computing and Communication Foundations CSE  Directorate for Computer and Information Science and Engineering
Start Date:	September 1, 2011
End Date:	October 31, 2012 (Estimated)
Total Intended Award Amount:	$229,193.00
Total Awarded Amount to Date:	$229,193.00
Funds Obligated to Date:	FY 2011 = $55,877.00
History of Investigator:	Cristinel Ababei (Principal Investigator) cristinel.ababei@marquette.edu
Recipient Sponsored Research Office:	North Dakota State University Fargo 1340 ADMINISTRATION AVE FARGO ND  US  58105 (701)231-8045
Sponsor Congressional District:	00
Primary Place of Performance:	North Dakota State University Fargo 1340 ADMINISTRATION AVE FARGO ND  US  58105
Primary Place of Performance Congressional District:	00
Unique Entity Identifier (UEI):	EZ4WPGRE1RD5
Parent UEI:	EZ4WPGRE1RD5
NSF Program(s):	Software & Hardware Foundation
Primary Program Source:	01001112DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s):	7923, 7941, 9150
Program Element Code(s):	779800
Award Agency Code:	4900
Fund Agency Code:	4900
Assistance Listing Number(s):	47.070

ABSTRACT

Future integrated circuits will contain tens, hundreds, or even thousand cores per chip. However, technology downscaling that can make this possible may also make the underlying hardware less reliable due to an increasing number of defects and wear out mechanisms. Therefore, one of the major problems facing the design of multiprocessor systems-on-chip is reliability. Because either the cores or the network-on-chip (used for communication between the cores) can become a reliability bottleneck for these systems, it is imperative that the reliability be addressed in a unified manner. To address the reliability challenge, this research develops a novel unified theoretical lifetime reliability modeling framework. This framework is based on efficient Monte Carlo methods to treat multiprocessor systems-on-chip as a combination of computation and communication units. The goal of this research is to develop new dynamic reliability management techniques based on dynamic voltage and frequency scaling and application remapping. Based on control theory concepts, these techniques proactively improve the lifetime reliability of multicore systems.

The proposed dynamic reliability management techniques enable the development of more reliable multiprocessor systems-on-chip, which have a dramatic impact on society via applications ranging from entertainment and gaming to bio-engineering, military and space. More broadly, the results of this project impact significantly the design of future integrated systems by advancing the understanding of the tradeoffs between reliability as a new design concern and power consumption, performance and area as traditional objectives.

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