| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
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| Initial Amendment Date: | December 21, 2010 |
| Latest Amendment Date: | April 27, 2015 |
| Award Number: | 1054830 |
| Award Instrument: | Continuing Grant |
| Program Manager: |
Almadena Chtchelkanova
achtchel@nsf.gov (703)292-7498 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | March 1, 2011 |
| End Date: | February 28, 2018 (Estimated) |
| Total Intended Award Amount: | $460,000.00 |
| Total Awarded Amount to Date: | $508,000.00 |
| Funds Obligated to Date: |
FY 2012 = $87,366.00 FY 2013 = $107,751.00 FY 2014 = $112,385.00 FY 2015 = $101,283.00 |
| History of Investigator: |
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| Recipient Sponsored Research Office: |
926 DALNEY ST NW ATLANTA GA US 30318-6395 (404)894-4819 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
926 DALNEY ST NW ATLANTA GA US 30318-6395 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): |
Software & Hardware Foundation, HIGH-PERFORMANCE COMPUTING |
| Primary Program Source: |
01001213DB NSF RESEARCH & RELATED ACTIVIT 01001314DB NSF RESEARCH & RELATED ACTIVIT 01001415DB NSF RESEARCH & RELATED ACTIVIT 01001516DB NSF RESEARCH & RELATED ACTIVIT |
| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Heterogeneous computer architectures, especially those that combine CPUs and GPUs, have become widespread in both desktop and mobile platforms. These architectures increase the complexity of architecture designs and the severity of resource management problems. To increase energy efficiency and performance in these architectures, this CAREER project investigates new resource management system that combines static and dynamic analysis. It uses analytical and statistical models to predict application performance and energy consumption behaviors. These models will be also used for exploiting heterogeneous architecture design choices. The proposed research brings together cross-disciplinary techniques from architecture, compiler, and power measurement systems, and researchers from academia and industry. The results of this research can be directly used for designing the next generations of heterogeneous architectures and software systems. The PI plans to collaborate with industrial partners to ensure a direct path for technology transfer.
In this project, the investigator plans to develop a new undergraduate course and a new simple GPU simulator framework for undergraduate students and graduate students. The proposed simulator will be available to a wide community of researchers.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
The increases in the amount of data and high compute-intensive applications such as machine learning applications have taken advantage of the recent advances in massively parallel architectures, especially GPUs. To support both traditional applications and emerging applications such as big data/graph/machine learning, combining CPUs and GPUs on the same chip has become a popular architecture trend. However, these heterogeneous architectures put more pressure on shared resource management. This research advances software and hardware solutions to the problems of managing shared resources.
The major intellectual outcomes of this program are several and focus on CPU+GPU/GPU modeling and resource management techniques that rely on CPU and GPU characteristic differences. First, we developed CPU+GPU timing simulators and distributed them as an open source. Second, we developed CPU+GPU power modeling. Third, we developed GPU analytical models to aid compilers’ optimizations or to speed up the architecture simulation so that big data applications can be also simulated. Fourth, we advanced the cache partitioning algorithm on CPU+GPU architectures. The solution introduced the concept of utilizing thread- level parallelism to decide the cache management schemes. Fifth, we analyzed recent applications such as graph applications and machine learning applications on both CPUs and GPUs and identified new performance bottlenecks on GPUs such as memory divergence problems or memory bandwidth issues. Finally, we developed an FPGA-based new GPU architecture course project for undergraduate students. These outcomes have enhanced the understanding of the CPU+GPU architectures and also improved the performance and power efficiency.
The engineering contributions of this program translated the preceding intellectual contributions into open source software artifacts to benefit the larger research and development community and enable further developments. These include i) CPU+GPU architecture simulators and ii) CPU and GPU versions of graph benchmarks. Collectively, the preceding intellectual and engineering contributions advance the state of the art CPU+GPU architecture designs and modeling.
Last Modified: 05/23/2018
Modified by: Hyesoon Kim
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