| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
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| Initial Amendment Date: | August 20, 2009 |
| Latest Amendment Date: | August 20, 2009 |
| Award Number: | 0916821 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Tao Li
CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | September 1, 2009 |
| End Date: | August 31, 2013 (Estimated) |
| Total Intended Award Amount: | $280,000.00 |
| Total Awarded Amount to Date: | $280,000.00 |
| Funds Obligated to Date: |
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| History of Investigator: |
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| Recipient Sponsored Research Office: |
341 PINE TREE RD ITHACA NY US 14850-2820 (607)255-5014 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
341 PINE TREE RD ITHACA NY US 14850-2820 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): | COMPUTER ARCHITECTURE |
| Primary Program Source: |
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| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Future multi-core microprocessors will be capable of deconfiguring faulty units in order to permit continued operation in the presence of wear-out failures. However, the unforeseen downside is pipeline imbalance in which other portions of the pipeline are now overprovisioned with respect to the deconfigured functionality. Such an imbalance leads to sub-optimal chip-wide power provisioning, since power is now allocated to pipeline functions that no longer provide the benefit they did with a fully functioning chip.
This research proposes to dynamically redistribute the chip power under pipeline imbalances that arise from deconfiguring faulty units. Through rebalancing -- achieved by temporary, symbiotic deconfiguration of additional functionality within the degraded core -- power is harnessed for use elsewhere on the chip. This additional power is dynamically transferred to portions of the multi-core chip that can realize a performance boost from turning on previously dormant microarchitectural features. The technical deliverables of this project will be: (1) a novel resilient multi-core system architecture -- including dynamic power redistribution management algorithms -- that achieves much higher performance than one that is oblivious to pipeline imbalances; and (2) detailed simulations that quantify this performance advantage for various multi-core workloads.
The broader impacts of this project relate to integrated research and education, enhanced infrastructure for research, broad dissemination of results, and potential societal impact. Furthermore, the PI will recruit women and underrepresented minority students to work on the project.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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