Award Abstract # 0916714
SHF: Small: Energy-Recycling VLSI Systems

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: REGENTS OF THE UNIVERSITY OF MICHIGAN
Initial Amendment Date: August 4, 2009
Latest Amendment Date: August 4, 2009
Award Number: 0916714
Award Instrument: Standard Grant
Program Manager: Sankar Basu
sabasu@nsf.gov
 (703)292-7843
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: August 1, 2009
End Date: July 31, 2013 (Estimated)
Total Intended Award Amount: $450,000.00
Total Awarded Amount to Date: $450,000.00
Funds Obligated to Date: FY 2009 = $450,000.00
ARRA Amount: $450,000.00
History of Investigator:
  • Marios Papaefthymiou (Principal Investigator)
    marios@uci.edu
Recipient Sponsored Research Office: Regents of the University of Michigan - Ann Arbor
1109 GEDDES AVE STE 3300
ANN ARBOR
MI  US  48109-1015
(734)763-6438
Sponsor Congressional District: 06
Primary Place of Performance: Regents of the University of Michigan - Ann Arbor
1109 GEDDES AVE STE 3300
ANN ARBOR
MI  US  48109-1015
Primary Place of Performance
Congressional District:
06
Unique Entity Identifier (UEI): GNJ7BBP73WE9
Parent UEI:
NSF Program(s): DES AUTO FOR MICRO & NANO SYST
Primary Program Source: 01R00910DB RRA RECOVERY ACT
Program Reference Code(s): 6890, 9216, 9217, 9218, HPCC
Program Element Code(s): 794500
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

"This award is funded under the American Recovery and Reinvestment Act of 2009
(Public Law 111-5)."

ID: 0916714
Papaefthymiou Marios
University of Michigan Ann Arbor
SHF:Small: Energy-Recycling VLSI Systems

This research project will investigate novel technologies for the design of very-large scale integrated (VLSI) computer systems that achieve unprecedented levels of energy-efficient operation through energy recycling. In contrast to conventional computer systems that consume all the energy supplied to them while computing, energy-recycling computers reclaim and reuse any energy that remains undissipated during their operation. Therefore, they have the potential to operate with substantially lower energy consumption than conventional computers. This project will encompass a broad spectrum of design technologies for energy-recycling computers, including circuitry, computing architectures, and design methodologies. The effectiveness of these technologies will be assessed through the design, fabrication, and experimental evaluation of proof-of-concept hardware prototypes.

With power consumption in high-performance microprocessors exceeding 100Watts, the design of energy-efficient computers has become a top priority in electronic design due to reliability concerns caused by excessive heat generation. Furthermore, energy-efficient computers play a key role in the development of new mobile applications due to battery-life considerations. And last, but not least, the power requirements of computing devices, including high-performance servers, desktops, and laptops, is placing an increasing burden on the power grid, with emissions from all these sources growing at a reported annual compound rate of 6% and thus posing a serious environmental concern. The outcomes of this research project can therefore be transformative, resulting in innovative design technologies for realizing next-generation computer systems that achieve unprecedented levels of reliable and energy-efficient operation, enable new mobile applications, and promote sustainability.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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Kao, J. C. Ma, W.-H. Sathe, V. S. Papaefthymiou, M. "Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic" IEEE Transactions on Very Large Scale Integration (VLSI) Systems , v.18 , 2011 , p.1 10.1109/TVLSI.2011.2140346
Kao, J. C. Ma, W.-H. Sathe, V. S. Papaefthymiou, M. "Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic" IEEE Transactions on Very Large Scale Integration (VLSI) Systems , v.20 , 2012 , p.977 10.1109/TVLSI.2011.2140346
Wei-Hsiang Ma; Kao, J.C.; Sathe, V.S.; Papaefthymiou, M.C.; "187 MHz Subthreshold-Supply Charge-Recovery FIR" Solid-State Circuits, IEEE Journal of , v.45 , 2010 , p.793 10.1109/JSSC.2010.2042247
Wei-Hsiang Ma; Kao, J.C.; Sathe, V.S.; Papaefthymiou, M.C.; "187 MHz Subthreshold-Supply Charge-Recovery FIR" Solid-State Circuits, IEEE Journal of , v.45 , 2010 , p.793 10.1109/JSSC.2010.2042247

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