| NSF Org: |
ECCS Division of Electrical, Communications and Cyber Systems |
| Recipient: |
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| Initial Amendment Date: | April 11, 2008 |
| Latest Amendment Date: | April 11, 2008 |
| Award Number: | 0801658 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Radhakisan Baheti
ECCS Division of Electrical, Communications and Cyber Systems ENG Directorate for Engineering |
| Start Date: | May 1, 2008 |
| End Date: | April 30, 2012 (Estimated) |
| Total Intended Award Amount: | $94,506.00 |
| Total Awarded Amount to Date: | $94,506.00 |
| Funds Obligated to Date: |
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| History of Investigator: |
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| Recipient Sponsored Research Office: |
926 DALNEY ST NW ATLANTA GA US 30318-6395 (404)894-4819 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
225 NORTH AVE NW ATLANTA GA US 30332-0002 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): | CCSS-Comms Circuits & Sens Sys |
| Primary Program Source: |
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| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.041 |
ABSTRACT
Integrative, Hybrid and Complex Systems
Anxiao Jiang, Texas Engineering Experiment Station
Jehoshua Bruck, California Institute of Technology
Paul E. Hasler, GA Tech Research Corporation - GA Institute of Technology
Christopher M. Twigg, SUNY at Binghamton
Collaborative Research: BRAM: Balanced RAnk Modulation for Data Storage in Next Generation Flash Memories
The objective of this research is to develop a new data storage technology for next-generation flash memories with substantially improved longevity, reliability and efficiency. The approach is to use the ranks of flash-cell levels to represent data, instead of using the absolute values of the cell levels. Novel techniques are studied, including elimination of cell over-programming, reduction or even elimination of block erasures, data modification, load balancing, and error correction. The research closely combines new information-theoretical methods and hardware design.
Intellectual Merit: The intellectual merit of this research includes laying the theoretical foundation for a new data-storage technology and designing a new hardware architecture for flash memories. The rank-modulation scheme eliminates the risk of charge over-injection and reduces block erasures, which are two major barriers to advances in flash memories. The theoretical analysis and the code designs have the potential to advance information theory. The study of hardware, including novel circuit components and testing techniques, has the potential to advance memory design.
Broader Impacts: Electronic memories are a widely used storage media, along with magnetic and optical media. Flash memories account for 90 percent of the non-volatile electronic memory market. Techniques that enable next-generation flash memory have the potential to make significant societal and economic impacts, with the possibility of benefiting industrial production, scientific research, and the large population of flash-memory users. This research integrates research and education by developing new courses, engaging students in advanced research, including students from under-represented groups, and disseminating new knowledge.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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