
NSF Org: |
CNS Division Of Computer and Network Systems |
Recipient: |
|
Initial Amendment Date: | August 12, 2021 |
Latest Amendment Date: | August 29, 2023 |
Award Number: | 2139167 |
Award Instrument: | Standard Grant |
Program Manager: |
Daniel Andresen
CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
Start Date: | October 1, 2021 |
End Date: | September 30, 2025 (Estimated) |
Total Intended Award Amount: | $299,735.00 |
Total Awarded Amount to Date: | $343,554.00 |
Funds Obligated to Date: |
FY 2023 = $43,819.00 |
History of Investigator: |
|
Recipient Sponsored Research Office: |
500 S LIMESTONE LEXINGTON KY US 40526-0001 (859)257-9420 |
Sponsor Congressional District: |
|
Primary Place of Performance: |
109 Kinkead Hall Lexington KY US 40526-0001 |
Primary Place of
Performance Congressional District: |
|
Unique Entity Identifier (UEI): |
|
Parent UEI: |
|
NSF Program(s): |
Special Projects - CNS, CSR-Computer Systems Research |
Primary Program Source: |
01002122DB NSF RESEARCH & RELATED ACTIVIT |
Program Reference Code(s): |
|
Program Element Code(s): |
|
Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.070 |
ABSTRACT
In the past decade, machine learning algorithms and models such as Deep Neural Networks (DNNs) have become increasingly prevalent for many emerging applications, such as medical prognosis, autonomous transportation, weather forecast, speech recognition and translation, image/video recognition and synthesis. This increasing prevalence has necessitated that the computing hardware platforms that process DNNs deliver consistently high performance and fast processing speeds. This need has driven computer hardware architects to design custom accelerator chips for processing DNNs. As researchers explore more sophisticated and powerful models of DNNs, the compute speed and throughput requirements from these DNN accelerator chips also increase. Traditional electronic implementations of DNN accelerator chips are breaking down under this pressure, which is catastrophic as it prevents the immediate widespread adoption of high-performance artificial intelligence that can transform society and improve lives. Fortunately, silicon photonics-based optical computing (OC) has emerged as an exciting paradigm that can replace slow electronic processing of DNNs with much faster, light-speed DNN processing. By processing DNNs directly in the optical domain, OC-based DNN accelerator chips have the potential to provide up to a thousand times faster processing speeds than traditional electronic chips. However, viable realization and deployment of OC-based DNN accelerators present enormous challenges, because the silicon-photonic building blocks of such accelerators consume very high static power, require excessively large silicon real estate, exhibit susceptibility to uncertainty induced errors, and lack flexibility. This project will involve transformative research to overcome these fundamental challenges and pave the way for realizing future OC-based DNN accelerator chips that are miniature in size, but possess the computing power to enable lower-cost, ultra-fast, and highly reliable processing of artificial intelligence tasks. Close collaborations with academic partners at the NSF NNCI node, Kentucky Multiscale, will aid in the rapid prototyping of the developed technology.
The key contribution of this project will be to design potentially groundbreaking architectures of OC-based DNN accelerators that will employ stochastic computing (SC) to realize various DNN processing functions. This project is critical early exploratory research because it focuses on a radically transformative goal of merging the disciplines of SC and OC in a highly synergistic manner for the important use case of DNN accelerator design. Such synergistic integration of SC and OC has never been explored before and involves interdisciplinary perspectives and new approaches that are considered to be more ?high risk-high payoff? than the typical research in CSR or other areas of CISE/NSF. The proposed synergistic integration of SC and OC will lay down a blueprint for realizing a new class of DNN accelerator architectures that will combine the processing speed benefits of OC with the area-efficiency, flexibility, static power efficiency, and error tolerance of SC, and be at the heart of the revolutionary artificial intelligence of the next generation to transform our lives in innumerable ways. Moreover, by exposing graduate students to the diverse aspects of stochastic arithmetic, probability theory, optical computing, nanofabrication, deep neural networks, and electro-optical characterization, this project will contribute towards an agile, high-tech workforce that will maintain continued US leadership in technological innovation.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Note:
When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external
site maintained by the publisher. Some full text articles may not yet be available without a
charge during the embargo (administrative interval).
Some links on this page may take you to non-federal websites. Their policies may differ from
this site.
Please report errors in award information by writing to: awardsearch@nsf.gov.