Revolutionizing Safety-Critical Systems: The SOSH Paradigm

This concluded grant has provided crucial support for the proposal and investigation of a new architectural paradigm for safety-critical platform design and consolidation, known as SOSH or Software-Shaped Platforms. We hereby review the foundational aspects of SOSH, its practical applications, and the envisioned capabilities to be explored in future work.

Foundational Aspects of SOSH

1. Introduction and Foundation

The SOSH paradigm represents a visionary approach to designing computing systems. It seeks to aid the transition of safety-critical systems into intelligent entities capable of interacting with their environment in a nuanced and adaptive manner. At its core, SOSH recognizes that safety and intelligence need to to be mutually exclusive. This paradigm shift acknowledges that the modern computing landscape demands more than just passive compliance with safety standards—it requires active engagement with real-world scenarios.

To reconcile safety and intelligence, the SOSH paradigm proposes to turn on-chip data-flows into programmatically manageable entities. Doing so exposes better control to the platform's system software about the use of performance-critical resources such as CPUs, accelerators, interconnects, and memory subsystems. This concluded grant has explored the possibility of defining foundational data-flow manipulation blocks in commercially available CPU+FPGA embedded systems.

2. Critical Enabling Mechanisms

- Partial Dynamic Reconfiguration (PDR)

PDR is a key enabler that allows hardware components within FPGA-based systems to be dynamically instantiated without requiring system resets. This capability opens the door to rapid and efficient hardware module swapping, providing the flexibility needed to adapt to changing requirements. 

- Programmable Logic In-the-Middle (PLIM)

PLIM represents a fundamental innovation within SOSH. It facilitates the rerouting of memory transactions through programmable logic, thereby enabling unprecedented levels of control over data flow within computing systems. PLIM extends the boundaries of traditional memory management, allowing for resource optimization, performance enhancement, and, crucially, self-awareness in computing systems.

- Coherence-Aided Elective and Seamless Alternative Routing (CAESAR)

CAESAR takes advantage of cache-coherent on-chip FPGAs to optimize memory traffic management. By leveraging cache-coherence and FPGAs, CAESAR enhances memory throughput and offers greater operational flexibility. This mechanism complements PLIM, further expanding the capabilities of SOSH.

Practical Applications of SOSH

SOSH has already been put into action through the development of concrete data flow operation blocks. These modules serve as proof of concept and demonstrate key data-flow manipulation primitives.

1. Scheduler in-the-Middle (SchIM)

SchIM is a configurable module that interposes itself between the last-level cache (LLC) of a CPU cluster and the memory controller, effectively managing memory transaction scheduling. Memory scheduling policies can be tailored at runtime, offering flexibility in memory management. We demonstrated the use of Time Division Multiple Access (TDMA), Fixed Priority (FP), and Traffic Shaping (TS). SchIM demonstrates how SOSH provides fine-grained control over data flow and allows for the definition of logic governing memory transactions from various upstream components to downstream components.

2. Relational Memory Engine (RME)

RME showcases the power of data flow reordering and filtering. Positioned between main memory and LLC, this configurable module transforms data on-the-fly from a row-major format to arbitrary column groups by leveraging the PLIM paradigm. Traditional data management systems often cater to either transactional or analytical workloads, necessitating data format conversions. RME breaks free from this limitation by creating reorganized aliases of data, allowing the CPU to access relational data with optimal spatial locality. This not only improves access efficiency but also reduces cache footprint. 

3. Silent Application Profiler

Coherence backstabbing and the CAESAR approach have paved the way for non-intrusive profiling and logging within SOSH. The Silent Application Profiler was introduced as a means to collect fine-grained metadata about main memory traffic generated by CPUs. By monitoring the coherence fabric, the profiler captures physical addresses and timestamps of cache line accesses that result in LLC cache misses. This passive monitoring approach incurs minimal overhead and offers valuable insights into application behavior, access patterns, and progress tracking.

Envisioned Capabilities of SOSH

 SOSH's journey is far from over, with envisioned capabilities pointing toward an even more intelligent and adaptable future for computing systems.

1. Progress Tracking and Behavior Prediction

Envisioned capabilities include the integration of progress tracking modules within SOSH platforms, allowing for proactive resource allocation and application behavior prediction.

2. Advanced Memory Models

SOSH platforms are set to redefine memory semantics with advanced models like historical memory and self-destructing memory. These memory models will introduce new levels of control and security to computing systems.

3. Security Threat Mitigation

SOSH platforms have great potential for allowing in-hardware behavior-based detection of malware activity. 
 

Conclusion

In conclusion, the grant's pioneering research efforts have not only established the SOSH paradigm but have also unlocked its immense potential across a spectrum of practical applications and envisioned capabilities. SOSH stands poised to usher in a new era of safety-critical systems characterized by intelligence, adaptability, and enhanced security, fundamentally reshaping the landscape of computing systems.

Last Modified: 11/19/2023
Modified by: Renato Mancuso