Award Abstract # 1901005
SHF: Medium: Collaborative Research: Statically Controlled Asynchronous Lane Execution (SCALE)

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: MICHIGAN TECHNOLOGICAL UNIVERSITY
Initial Amendment Date: September 10, 2019
Latest Amendment Date: August 26, 2021
Award Number: 1901005
Award Instrument: Continuing Grant
Program Manager: Almadena Chtchelkanova
achtchel@nsf.gov
 (703)292-7498
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: September 15, 2019
End Date: August 31, 2025 (Estimated)
Total Intended Award Amount: $599,544.00
Total Awarded Amount to Date: $735,170.00
Funds Obligated to Date: FY 2019 = $246,329.00
FY 2021 = $488,841.00
History of Investigator:
  • Soner Onder (Principal Investigator)
    soner@mtu.edu
Recipient Sponsored Research Office: Michigan Technological University
1400 TOWNSEND DR
HOUGHTON
MI  US  49931-1200
(906)487-1885
Sponsor Congressional District: 01
Primary Place of Performance: Michigan Technological University
1400 Townsend Drive
Houghton
MI  US  49931-1295
Primary Place of Performance
Congressional District:
01
Unique Entity Identifier (UEI): GKMSN3DA6P91
Parent UEI: GKMSN3DA6P91
NSF Program(s): CISE Education and Workforce,
Special Projects - CCF,
Software & Hardware Foundation
Primary Program Source: 01001920DB NSF RESEARCH & RELATED ACTIVIT
01002122DB NSF RESEARCH & RELATED ACTIVIT

01002223DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 2878, 7482, 7924, 7942, 9251
Program Element Code(s): 055Y00, 287800, 779800
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

Enabling better performing systems benefits applications that span those running on mobile devices to large data applications running on data centers. The efficiency of most applications is still primarily affected by single thread performance. Instruction-level parallelism (ILP) speeds up programs by executing instructions of the program in parallel, with 'superscalar' processors achieving maximum performance. At the same time, energy efficiency is a key criteria to keep in mind as such speedup happens, with these two being conflicting criteria in system design. This project develops a Statically Controlled Asynchronous Lane Execution (SCALE) approach that has the potential to meet or exceed the performance of a traditional superscalar processor while approaching the energy efficiency of a very long instruction word (VLIW) processor. As implied by its name, the SCALE approach has the ability to scale to different types and levels of parallelism. The toolset and designs developed in this project will be available as open-source and will also have an impact on both education and research. The SCALE architectural and compiler techniques will be included in undergraduate and graduate curricula.

The SCALE approach supports separate asynchronous execution lanes where dependencies between instructions in different lanes are statically identified by the compiler to provide inter-lane synchronization. Providing distinct lanes of instructions allows the compiler to generate code for different modes of execution to adapt to the type of parallelism that is available at each point within an application. These execution modes include explicit packaging of parallel instructions, parallel and pipelined execution of loop iterations, single program multiple data (SPMD) execution, and independent multi-threading.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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Mortensen, Abigail and Pomerville, Scott and Whalley, David and Onder, Soner and Uh, Gang-Ryung "Facilitating the Bootstrapping of a New ISA" Languages, Compilers, and Tools for Embedded Systems , 2023 https://doi.org/10.1145/3589610.3596282 Citation Details
Stokes, Michael and Whalley, David and Onder, Soner "Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache" ACM transactions on architecture and code optimization , v.18 , 2021 https://doi.org/3449043 Citation Details

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