Award Abstract # 1844952
CAREER: Advancing STTRAM Caches for Runtime Adaptable and Energy-Efficient Microarchitectures

NSF Org: CNS
Division Of Computer and Network Systems
Recipient: UNIVERSITY OF ARIZONA
Initial Amendment Date: April 25, 2019
Latest Amendment Date: May 4, 2023
Award Number: 1844952
Award Instrument: Continuing Grant
Program Manager: Marilyn McClure
mmcclure@nsf.gov
 (703)292-5197
CNS
 Division Of Computer and Network Systems
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: June 1, 2019
End Date: May 31, 2025 (Estimated)
Total Intended Award Amount: $500,000.00
Total Awarded Amount to Date: $532,000.00
Funds Obligated to Date: FY 2019 = $94,349.00
FY 2020 = $113,067.00

FY 2021 = $99,890.00

FY 2022 = $118,822.00

FY 2023 = $105,872.00
History of Investigator:
  • Tosiron Adegbija (Principal Investigator)
    tosiron@arizona.edu
Recipient Sponsored Research Office: University of Arizona
845 N PARK AVE RM 538
TUCSON
AZ  US  85721
(520)626-6000
Sponsor Congressional District: 07
Primary Place of Performance: University of Arizona
888 N Euclid Ave
Tucson
AZ  US  85719-4824
Primary Place of Performance
Congressional District:
07
Unique Entity Identifier (UEI): ED44Y3W6P7B9
Parent UEI:
NSF Program(s): Special Projects - CNS,
CSR-Computer Systems Research
Primary Program Source: 01002223DB NSF RESEARCH & RELATED ACTIVIT
01001920DB NSF RESEARCH & RELATED ACTIVIT

01002021DB NSF RESEARCH & RELATED ACTIVIT

01002122DB NSF RESEARCH & RELATED ACTIVIT

01002223DB NSF RESEARCH & RELATED ACTIVIT

01002324DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 1045, 9251
Program Element Code(s): 171400, 735400
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

On-chip caches are important due to their substantial impact on the energy consumption and performance of a wide variety of computer systems, including desktop computers, embedded systems, mobile devices, servers, etc. As an alternative to traditional static random-access memory (SRAM) for implementing caches, the spin-transfer torque RAM (STTRAM) is a type of non-volatile memory that promises several advantages, such as high density, low leakage, high endurance, and compatibility with complementary metal-oxide-semiconductor (CMOS). However, STTRAM caches still face critical challenges that impede their widespread adoption, such as high write latency and energy. In addition, users of computer systems and the programs that run on the systems typically have variable resource requirements, necessitating caches that can dynamically adapt to runtime needs.

This CAREER project will investigate several interrelated research problems, including: STTRAM's characteristics and how they can be leveraged for improving the energy efficiency and performance of computer systems that run diverse programs; techniques for improving the user's experience while running the programs; new architectures and management techniques for enabling STTRAM caches that are energy-efficient and can dynamically adapt to running programs? individual needs; and novel methods to address the challenges of implementing STTRAM caches in complex multicore computer systems. Ultimately, the project will develop STTRAM cache architectures that can automatically adapt to the execution needs of diverse programs, resulting in more energy-efficient and faster computer systems.

The project's broader impacts include architectures and methods that will improve the performance and energy efficiency of a wide variety of computer systems for running a wide variety of programs. With the growth of the Internet of Things (IoT), spanning diverse computing and user needs, this project represents an important and necessary step towards adaptable and low-overhead computer systems. This CAREER project also seeks to foster education and diversity in science, technology, engineering, and math (STEM) fields through K-12 seminars, and by engaging and equipping a diverse group of young engineers with necessary techniques and skills to design innovative solutions for energy-efficient and adaptable Internet of Things architectures.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 11)
Aliyev, Ilkin and Svoboda, Kama and Adegbija, Tosiron "Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems , v.13 , 2023 https://doi.org/10.1109/JETCAS.2023.3327746 Citation Details
Cordeiro, Renato and Gajaria, Dhruv and Limaye, Ankur and Adegbija, Tosiron and Karimian, Nima and Tehranipoor, Fatemeh "ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , v.39 , 2020 https://doi.org/10.1109/TCAD.2020.3012169 Citation Details
Dhruv Gajaria and Tosiron Adegbija "Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing" Journal of signal processing systems for signal image and video technology , 2021 https://doi.org/https://doi.org/10.1007/s11265-021-01682-y Citation Details
Gajaria, Dhruv and Adegbija, Tosiron "ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors" Proceedings of the International Symposium on Memory Systems (MEMSYS), 2019 , 2019 10.1145/3357526.3357553 Citation Details
Gajaria, Dhruv and Adegbija, Tosiron "Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads" Future Generation Computer Systems , v.136 , 2022 https://doi.org/10.1016/j.future.2022.05.023 Citation Details
Gajaria, Dhruv and Antony Gomez, Kevin and Adegbija, Tosiron "A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy" 2022 IEEE 40th International Conference on Computer Design (ICCD) , 2022 https://doi.org/10.1109/ICCD56317.2022.00105 Citation Details
Gajaria, Dhruv and Kuan, Kyle and Adegbija, Tosiron "SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning" 2019 Tenth International Green and Sustainable Computing Conference (IGSC) , 2019 10.1109/IGSC48788.2019.8957182 Citation Details
Kuan, Kyle and Adegbija, Tosiron "A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches" 2020 IEEE 38th International Conference on Computer Design (ICCD) , 2020 https://doi.org/10.1109/ICCD50377.2020.00051 Citation Details
Kuan, Kyle and Adegbija, Tosiron "A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation" 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2022 https://doi.org/10.1109/ISVLSI54635.2022.00026 Citation Details
Kuan, Kyle and Adegbija, Tosiron "Energy and Performance Analysis of STTRAM Caches for Mobile Applications" 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) , 2019 10.1109/MCSoC.2019.00044 Citation Details
Yusuf, Alaba and Adegbija, Tosiron and Gajaria, Dhruv "Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey" IEEE Access , v.12 , 2024 https://doi.org/10.1109/ACCESS.2024.3365632 Citation Details
(Showing: 1 - 10 of 11)

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