| NSF Org: |
CNS Division Of Computer and Network Systems |
| Recipient: |
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| Initial Amendment Date: | April 25, 2019 |
| Latest Amendment Date: | May 4, 2023 |
| Award Number: | 1844952 |
| Award Instrument: | Continuing Grant |
| Program Manager: |
Marilyn McClure
mmcclure@nsf.gov (703)292-5197 CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | June 1, 2019 |
| End Date: | May 31, 2025 (Estimated) |
| Total Intended Award Amount: | $500,000.00 |
| Total Awarded Amount to Date: | $532,000.00 |
| Funds Obligated to Date: |
FY 2020 = $113,067.00 FY 2021 = $99,890.00 FY 2022 = $118,822.00 FY 2023 = $105,872.00 |
| History of Investigator: |
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| Recipient Sponsored Research Office: |
845 N PARK AVE RM 538 TUCSON AZ US 85721 (520)626-6000 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
888 N Euclid Ave Tucson AZ US 85719-4824 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): |
Special Projects - CNS, CSR-Computer Systems Research |
| Primary Program Source: |
01002223DB NSF RESEARCH & RELATED ACTIVIT 01002324DB NSF RESEARCH & RELATED ACTIVIT 01002223DB NSF RESEARCH & RELATED ACTIVIT 01002021DB NSF RESEARCH & RELATED ACTIVIT 01002122DB NSF RESEARCH & RELATED ACTIVIT |
| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
On-chip caches are important due to their substantial impact on the energy consumption and performance of a wide variety of computer systems, including desktop computers, embedded systems, mobile devices, servers, etc. As an alternative to traditional static random-access memory (SRAM) for implementing caches, the spin-transfer torque RAM (STTRAM) is a type of non-volatile memory that promises several advantages, such as high density, low leakage, high endurance, and compatibility with complementary metal-oxide-semiconductor (CMOS). However, STTRAM caches still face critical challenges that impede their widespread adoption, such as high write latency and energy. In addition, users of computer systems and the programs that run on the systems typically have variable resource requirements, necessitating caches that can dynamically adapt to runtime needs.
This CAREER project will investigate several interrelated research problems, including: STTRAM's characteristics and how they can be leveraged for improving the energy efficiency and performance of computer systems that run diverse programs; techniques for improving the user's experience while running the programs; new architectures and management techniques for enabling STTRAM caches that are energy-efficient and can dynamically adapt to running programs? individual needs; and novel methods to address the challenges of implementing STTRAM caches in complex multicore computer systems. Ultimately, the project will develop STTRAM cache architectures that can automatically adapt to the execution needs of diverse programs, resulting in more energy-efficient and faster computer systems.
The project's broader impacts include architectures and methods that will improve the performance and energy efficiency of a wide variety of computer systems for running a wide variety of programs. With the growth of the Internet of Things (IoT), spanning diverse computing and user needs, this project represents an important and necessary step towards adaptable and low-overhead computer systems. This CAREER project also seeks to foster education and diversity in science, technology, engineering, and math (STEM) fields through K-12 seminars, and by engaging and equipping a diverse group of young engineers with necessary techniques and skills to design innovative solutions for energy-efficient and adaptable Internet of Things architectures.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
This CAREER project advanced the state of the art in adaptable and energy-efficient Spin-Transfer Torque RAM (STTRAM) caches for resource-constrained multicore systems. The research addressed three key challenges that have historically limited the widespread adoption of STTRAM in on-chip caches: (1) understanding application-driven sensitivity to STTRAM characteristics, (2) developing techniques for logical adaptability in multi-level STTRAM caches, and (3) addressing fundamental architectural challenges in designing STTRAM-based caches and systems (e.g., in-memory computing).
The project developed and evaluated novel frameworks for runtime adaptability in STTRAM caches, focusing on adapting retention time and cache management policies to dynamic application and user behavior. These frameworks incorporated workload characterization across a wide spectrum of applications—ranging from healthcare and IoT to machine learning and multiprogrammed/multithreaded workloads—and leveraged simulation platforms such as GEM5, NVSim, and FPGA-based prototypes for validation. Key innovations included:
- Logical Adaptable Retention Time (LARS) architectures that dynamically match cache retention times to application needs, reducing energy consumption without performance degradation.
- Techniques to significantly lower refresh overheads in relaxed-retention STTRAM caches, leveraging STTRAM’s density for intra-cache refresh rather than external buffers.
- Adaptable last-level STTRAM cache designs that optimize retention time assignments at a fine granularity (e.g., per cache way), based on observed workload patterns.
- New hierarchical in-memory computing system architectures to enable better efficiency of in-memory computing by incorporating heterogeneous compute units across multiple levels of the memory hierarchy.
The research yielded substantial quantitative improvements. For example, across diverse benchmarks, extensive experimental evaluations showed that the proposed adaptable cache architectures achieved significant energy savings relative to SRAM and prior STTRAM approaches (e.g., 35.8% savings from LARS; 60.6% savings from adaptable last-level STTRAM cache)—while maintaining or improving performance. These results directly support the design of future cache hierarchies for mobile, embedded, and IoT systems, as well as high-performance heterogeneous processors.
Beyond technical contributions, the project achieved significant broader impacts in workforce development and STEM education:
- Graduate Student Support and Training: The project provided support for three Ph.D. students, all of whom have since graduated and are working in industry or academia in roles that draw directly on the skills developed during the project. Their dissertations and publications contributed to the research community’s understanding of energy-efficient, adaptable cache architectures.
- Undergraduate Research Opportunities: Through NSF REU supplements, the project supported six undergraduate students, offering them hands-on experience in architecture modeling, memory system design, and experimental evaluation. Several of these students pursued graduate study or industry positions in computer engineering.
- Publications and Dissemination: Work supported by this project contributed to over 20 publications in top-tier conferences and journals, including DATE, ASPDAC, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Transactions on Computers and ICCAD. These publications have broadened the impact of the research by making the methods, models, and insights available to the global community.
- Educational Integration: Results from the project were incorporated into undergraduate and graduate courses on computer architecture and embedded systems at the University of Arizona, helping to train the next generation of computer engineers.
In addition, the project’s simulation frameworks and hardware designs were made available to the research community, enabling reproducibility and accelerating further innovation in adaptable memory system design.
Overall, this CAREER project has established a foundation for runtime-adaptable STTRAM-based caches that can intelligently balance performance and energy efficiency. It has produced widely cited publications, trained highly skilled graduates now contributing to the field, and delivered tangible tools and insights to both academia and industry. The approaches developed here are expected to remain relevant as emerging memory technologies mature and the demand for energy-efficient computing continues to grow across domains such as AI, IoT, and mobile systems.
Last Modified: 08/04/2025
Modified by: Tosiron Adegbija
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