
NSF Org: |
CNS Division Of Computer and Network Systems |
Recipient: |
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Initial Amendment Date: | September 13, 2018 |
Latest Amendment Date: | April 25, 2019 |
Award Number: | 1836901 |
Award Instrument: | Standard Grant |
Program Manager: |
Deepankar Medhi
dmedhi@nsf.gov (703)292-2935 CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
Start Date: | October 1, 2018 |
End Date: | September 30, 2021 (Estimated) |
Total Intended Award Amount: | $300,000.00 |
Total Awarded Amount to Date: | $316,000.00 |
Funds Obligated to Date: |
FY 2019 = $16,000.00 |
History of Investigator: |
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Recipient Sponsored Research Office: |
3 RUTGERS PLZ NEW BRUNSWICK NJ US 08901-8559 (848)932-0150 |
Sponsor Congressional District: |
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Primary Place of Performance: |
671 US Highway 1 North Brunswick NJ US 08902-3390 |
Primary Place of
Performance Congressional District: |
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Unique Entity Identifier (UEI): |
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Parent UEI: |
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NSF Program(s): | Special Projects - CNS |
Primary Program Source: |
01001920DB NSF RESEARCH & RELATED ACTIVIT |
Program Reference Code(s): |
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Program Element Code(s): |
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Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.070 |
ABSTRACT
Wireless networks have grown enormously during the past 30 years, impacting numerous industries, including telecommunications, emergency response, and entertainment. Wireless advances could radically change several industries in the near future, including manufacturing, the automotive industry, healthcare, assisted living, public events, home automation, and utilities. However, each industry has different, often opposing, wireless demands. Manufacturing often requires a low data rate, ultra-low latency closed loop communication between machines, while emerging augmented reality interactions between people have much larger large data volumes, but can tolerate higher latency. Today, applications and services are constrained to a handful of wireless technologies, such as 4G, Wi-Fi and Bluetooth, because developing and modifying new radio protocols requires many man-years. The challenge for the wireless community is to enable wireless networks the same flexibility as regular computing devices, such as laptops or phones, where the same hardware supports a near infinite variety of behaviors realized in software. Flexibility at the wireless level has lagged as radios have been implemented as fixed-function circuits, in order to minimize marginal cost, energy use, and network latency. Enabling such flexibility would open opportunities for new wireless functions in diverse application domains.
While the emerging field of Software-Defined Radio (SDR) has made progress toward this vision, recent results have shown that traditional SDRs suffer serious limitations. The main problem is the slower sequential execution, even when using multicore central processing units (CPUs) or graphics processing units (GPUs), in contrast to the fast execution and high parallelization in application-specific integrated circuits (ASICs)or field-programmable gate arrays (FPGAs). This research will explore and evaluate a new software abstraction, Dynamic Blocks (DB), which will realize many software abstractions in an SDR FPGA, including procedure calls, recursion, queuing, dynamic routing, shared memory and matrix algebra. Realizing these abstractions in FPGAs will allow developers to rapidly try new designs or modify existing ones while meeting real-time latency and low energy requirements. The project will use millimeter-wave (mmWave) scenarios to evaluate real-time SDRs programmed using DBs. The SDRs available in the ORBIT testbed at Rutgers University, and the future mmWave capable equipment from the recently-funded COSMOS platform and European Union partners would be the target platforms for this research.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
The ICE-T project seeks three major enhancements to the set of ORCA project developed tools to lower the barrier for high performance, real-time experimentation in the area of radio and wireless technology. Specifically, we explored three different parallelization approaches to speed up Software Defined Radios (SDR). As SDR implement radio functions in software rather than analogy circuits, they have tight latency requirements to keep packet response times to within protocol specifications. We investigated using Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and parallel CPUs using the Message Passing Interface as parallelization environments. We found all three can gain performance over standard SDR software. The research is a joint collaboration between the ORBIT and COSMOS (PAWR) teams at Rutgers, and teams from the ORCA Consortium that include, IMEC and Katholieke Univeriteit Leuven in Belgium, Trinity College Dublin in Ireland, Technische Universitaet Dresden and National Instruments Dresden GMBH in Germany, and Martel Innovate in Switzerland as well as ORCA Open Call collaborators including Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) - CERCA in Spain, IMDEA Networks Institute in Spain, and University of Skopje in North Macedonia.
The first project explored novel method to accelerate software radios by placing more of the functionality in the FPGA rather than in the host CPU. One example function we moved into the FPGA is a Correlator. We implemented 3 new functional blocks in the FPGA. On the transmit side, we added a spreader block, and on the receiver side we added an averaging block and a correlator block. We found the FPGA resources taken up with the new blocks was modest, adding 11.4%, 8.74% and 2.76% extra to the LUT, Flip-Flop, and BRAM resources, respectively. By moving the correlator and averaging blocks to the FPGA,the processing time on the host, and amount of data transferred from the SDR to the host was significantly reduced. This made channel sounding experiments much easier as the results such as can now be observed real time, as opposed to waiting for off-line results.
In the second project, significant progress was made in introducing GPUs as accelerators for demodulation of Massive MIMO (Multiple Input Multiple Output) next generation wireless systems. The issue with SDRs is that the volume of data scaling linearly with the number of antennas, and each antenna can generate on the order of 0.5 to 10 GBs of RF samples. While an FPGA could have been used, a GPU is much more easily programmable and has the required parallelization to increase the speed of computation.
While performing experimentation with the our GPU platform, we found that for certain demodulation scenarios, using a CPU was faster when the number of antennas was low, typically less than 2 or 4. However, as the number of antennas increases the GPU is always faster, by up to 0.6 to 3 times faster depending on the demodulation used.
The third project used distributed memory message passing model by using Message Passing Interface (MPI) to distribute the encoding and Sum-Product decoding processes of LDPC codes over multiple multi-core CPUs. We performed the processing using stream processing and batch processing mechanisms. We showed the acceleration provided by using message passing model for both mechanisms, and compare the execution time required for processing with respect to increases in both the number of CPUs and cores per CPU. We also found that while using a distributed memory based message passing model for distributed processing provides acceleration, increasing the number of processors to more than the logical cores in the system adds high processing latency as well as inter-processor communication latency due to context switching between processes.
In the final year, the project research objectives were expanded to include evaluation of the accuracy of machine learning structures in modulation recognition. Our machine learning techniques included conventional and non-conventional neural networks, and experimentation aimed at examination of impact of complexity, training time and noise conditions on performance. The results indicate that the CNN provides the best accuracy but it is time and resource intensive and that the FCN is the optimal network in terms of timing and resources and exhibits accuracy results comparable to the CNN network.
In addition to these ICE-T projects, the team actively participated in various ORCA project activities including supporting external ORCA Open Call participants performing development and experimentation on the ORBIT and, more recently on COSMOS testbeds. Also, the core of the ORCA project team (imec and Rutgers) formed the Scatter Team that competed in the DARPA Spectrum Collaboration Challenge. Once the ORCA project ended, the team continued international collaboration by supporting various NGI Atlantic evaluation projects that are being performed on ORBIT and COSMOS testbeds.
Last Modified: 01/31/2022
Modified by: Ivan Seskar
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