| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
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| Initial Amendment Date: | July 5, 2018 |
| Latest Amendment Date: | May 8, 2023 |
| Award Number: | 1755981 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Sankar Basu
sabasu@nsf.gov (703)292-7843 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | July 1, 2018 |
| End Date: | May 31, 2024 (Estimated) |
| Total Intended Award Amount: | $175,000.00 |
| Total Awarded Amount to Date: | $175,000.00 |
| Funds Obligated to Date: |
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| History of Investigator: |
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| Recipient Sponsored Research Office: |
1125 W MAPLE ST STE 316 FAYETTEVILLE AR US 72701-3124 (479)575-3845 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
504 JB Hunt Fayetteville AR US 72701-1201 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): |
Software & Hardware Foundation, EPSCoR Co-Funding |
| Primary Program Source: |
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| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
With the slowing down of Moore's Law, it is challenging to integrate more transistors and features into a single chip. New system- and package-level techniques are critical for emerging mobile and Internet of Things (IoT) applications with a strong emphasis on power and cost. This research aims to develop the key models and Computer-Aided Design (CAD) tools to enable integrating various heterogeneous components into a single Fanout Wafer-Level Package. It will address the major challenge of maintaining signal integrity and electro-thermal reliability in a powerful, yet compact, system with multiple Integrated Circuits (ICs) closely packed together to improve energy and cost efficiency. Moreover, a graduate course on CAD and physical design will be offered at the University of Arkansas. The developed CAD framework will be open-sourced and publicly available to further stimulate the advancement in chip-package co-design tool flow and commercialization.
With heterogeneous components tightly integrated, new parasitics, resulting from both electrical- and magnetic-coupling, require both IC and package designers to work together closely on circuit and physical design. The proposed CAD framework blurs the boundaries between chip and package layouts in the design flow and extracts major coupling elements between them. It integrates chip-package co-design techniques into the entire VLSI design flow with time-efficient computational models so that signal integrity issues can be captured and addressed early to avoid a time-consuming trial-and-error design process. All parasitic components such as coupling capacitance and mutual inductance are included to ensure accurate timing and noise analyses. The new modeling methods, CAD algorithms and flows, and optimization techniques address the principle motivation behind more-than-Moore technologies and move toward high-density and energy-efficient heterogeneous systems.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
This project aims to design Electronic Design Automation (EDA) tools for high-performance, high-density, heterogeneous chiplet designs. Multi-Chip Fan-Out Wafer-Level-Packaging (WLP) is an advanced packaging technology integrating multiple chiplets into a high-density system-in-package with excellent performance and energy efficiency. The developed EDA platform enables agile chiplet design optimization by automating placement, routing, optimization, and verification of heterogeneous system-in-package. The cross-boundary design flow further bridges the gap between two traditionally separated communities: ASIC and package engineers.
The targets of this project include: (1) Enable the design and extraction of both chiplets and the package altogether using a unified design environment; (2) Integrate heterogeneous systems with different technologies; (3) Support parasitic extraction with inductive elements for signal and power integrity optimization; (4) Validate the netlist-to-layout physical design with performance, power, and area (PPA) optimizations.
To summarize our research outcome: (1) We designed a 2.5D redistribution layer (RDL) planner that analyzes all chiplet netlists, geometry, and design constraints and generates the package floorplan, chiplet pin configurations, RDL routing, and package wire-load models; (2) We designed new EDA flows for chiplet-package co-design. The traditional die-by-die black-box flow implements each chiplet independently, ignoring the inter-chiplet and cross-boundary parasitics. Our holistic white-box flow integrates all chiplets and package layers into a single environment and captures all the interactions between the chip and package wires. It is best suited for homogeneous chiplet designs aiming at maximum accuracy. Further, we developed a novel in-context gray-box flow for heterogeneous chiplet integration. It also enables collaborative designs and addresses IP-protection concerns, exposing only necessary interface layers. (3) We developed an inductance-aware timing model that accurately models the signal delay and extends existing Static Timing Analysis (STA) tools. This inductance-aware timing model is used to develop our chiplet-package timing optimization flow, where the RDL RLC delay is analyzed along with chiplet RC parasitics. It is further integrated into our holistic and in-context design flows to perform PPA optimization in physical design; (4) Using our chiplet-package co-design flows, we designed an ARM Cortex-M microcontroller comparing the 2D with 2.5D implementations. We first implemented it in a 45nm open-source process to test our EDA flow, then redesigned it in the TSMC 65nm process for real silicon tape-out. The top metal layers are modified following the TSMC 2.5D InFO WLP technology configurations. We successfully taped out both 2D and 2.5D designs and validated all functionality and performance in silicon.
All project objectives and measurable outcomes have been achieved successfully with our EDA flows and chiplet-package designs.
Last Modified: 10/17/2024
Modified by: Yarui Peng
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