
NSF Org: |
ECCS Division of Electrical, Communications and Cyber Systems |
Recipient: |
|
Initial Amendment Date: | July 12, 2017 |
Latest Amendment Date: | July 12, 2017 |
Award Number: | 1745364 |
Award Instrument: | Standard Grant |
Program Manager: |
John Zhang
ECCS Division of Electrical, Communications and Cyber Systems ENG Directorate for Engineering |
Start Date: | July 15, 2017 |
End Date: | June 30, 2020 (Estimated) |
Total Intended Award Amount: | $79,532.00 |
Total Awarded Amount to Date: | $79,532.00 |
Funds Obligated to Date: |
|
History of Investigator: |
|
Recipient Sponsored Research Office: |
4000 CENTRAL FLORIDA BLVD ORLANDO FL US 32816-8005 (407)823-0387 |
Sponsor Congressional District: |
|
Primary Place of Performance: |
4000 Central Florida Blvd. Orlando FL US 32816-8005 |
Primary Place of
Performance Congressional District: |
|
Unique Entity Identifier (UEI): |
|
Parent UEI: |
|
NSF Program(s): | CCSS-Comms Circuits & Sens Sys |
Primary Program Source: |
|
Program Reference Code(s): |
|
Program Element Code(s): |
|
Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.041 |
ABSTRACT
The parallel recordings from large neuron populations in the sensory cortex and primary motor cortex reveal the rich information encoded into neural signals, and guide research in restoring cognitive and motor behaviors. In such devices, the quality of information relies on the density of neural signals being recorded. The recording density in the current brain-machine interface remains insufficient to be clinically relevant and significant improvements are required to help severely disabled patients to fully regain mobility or other impaired functions. However, the lack of technology to accommodate the massive wire counts between electrode-amplifier pairs and the complexity in the hermetic packaging in implant devices present large challenges in moving forward beyond 1000 channels to be clinically relevant. This Early-concept Grant for Exploratory Research (EAGER) project will investigate a transformative approach to design a wireless neural interface system by integrating the entire wireless neural system into a thin silicon substrate, and, thus, introduce an avenue for developing a scalable neural interface system for future brain-machine interface research and clinical use. The success of this exploratory study will transform the design approach taken by brain-machine interface developers, which involves the use of external wires for interconnections and thus complicates the packaging, and will have an immediate impact in research studies focused on cognitive and motor behaviors that demands the extraction of high density neural recordings directly from the cortex to guide the neural prosthetics. It will also significantly lower the manufacturing cost by fabricating the device using common semiconductor fabrication methods, which may result in more affordable neural prosthetics for patients in need.
Fully-implantable neural interface systems are designed with a complex integration of many components including: electrode arrays, amplifiers, processors, wireless transmitters, and a battery. Every existing system uses wire feedthroughs to establish electrical connections between the components, and the connections are insulated with casing/packaging to prevent leakage during implant. This method presents many limitations: the scalability is severely limited by the number of feedthroughs available, the runtime is limited to the battery capacity, the metal casing can impede wireless transmissions, the long-term durability is questionable with non-metallic packaging, and the bulky implant device complicates the surgical procedure and introduces discomfort/risks to patients. Thus, the development of a new brain-machine interface with large-scale recording capability are needed to advance basic brain research, large-scale brain mapping and clinical translations of brain-machine interface. This project aims to monolithically integrate a 1000-ch neural interface system in a silicon substrate. The monolithic integration of every component into a single silicon die enables high-density recordings by eliminating external wires and linking all the electronic interconnections using sub-micron interconnects in integrated circuits. This approach yields unprecedented advantages, compared to the conventional approach, including the design simplicity and the elimination of complex packaging. The study is composed of the following efforts: (1) On-chip integration of the pillar electrode array, (2) Backplane integration of RF planar coils and capacitors, and (3) Design of low-power small footprint amplifier array and peripheral circuitries for high-throughput neural recordings.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Note:
When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external
site maintained by the publisher. Some full text articles may not yet be available without a
charge during the embargo (administrative interval).
Some links on this page may take you to non-federal websites. Their policies may differ from
this site.
PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
In this project, we proposed a bold and high risk/high reward concept, a monolithic integration of neural interface system on a silicon die, to overcome limitations in current brain-machine interface (BMI) systems and to build a concrete foundation for an extremely scalable neural interface system that is currently in demand for the BMI’s clinical use. The goal of this project is to develop and test the monolithic integration method. Three aims were proposed to accomplish the goal with two sub-aims for each aim.
From this project, three main outcomes were generated. (1) All-integrated monolithic chip has been successfully designed and fabricated using 0.35-µm CMOS process to test the monolithic approach for a neural interface. The chip consists of 1024 on-chip amplifiers, 1024 on-chip electrodes, on-chip wireless power coil, on-chip wireless data coil, and transmitter, voltage regulator, and rectifier. Each amplifier occupies 75 µm × 75 µm area and the entire chip occupies 3.8 mm × 3.8 mm. (2) We develop an automated design method for planar square-spiral coils that generates the idealized design parameters for maximum power transfer efficiency according to the input design requirements. (3) In additional, we have also developed a 1024-ch neurochemical sensor for directly interfacing with neurons as an alternative method to the conventional action potential measurements. The neurochemical sensor was successfully developed, and the sensor was capable of detecting neurochemical release directly from cells.
Last Modified: 11/19/2020
Modified by: Brian N Kim
Please report errors in award information by writing to: awardsearch@nsf.gov.