The goals of the project were to develop mechanisms to support atomic and durable concurrent transactions in emerging persistent memory devices, exemplified by the recent Apache Pass memory chips from Intel. These devices have capacity, speed, and power advantages over traditional block-based non-volatile media, and can be addressed directly by the programmer at word granularity using Load and Store instructions. This fast, direct access to non-volatile storage is at odds with existing transactional systems; in traditional systems, the low speed of the IO devices permit these accesses to be mediated by costly operating system or dedicated database management software. However, with persistent memory, applications must now deal with ensuring the consistency of the persistent medium in the presence of unexpected aborts caused by failures or exceptions.

Several solutions for durable transaction support were developed in the project based on the idea of Write-aside Persistence (WrAP). WrAP aims to allow applications to execute at near-native speeds using the processor caches, while relegating persistence operations to the background. A software implementation was developed and embodied in a library called SoftWrap; the approach uses aliasing and redo logging to ensure atomicity by preventing untimely cache evictions from corrupting persistent memory. Another solution was based on employing simple hardware support in the memory controller to regulate the times at which evicted cache lines can be safely written back to persistent memory. In these solutions, isolation between concurrent threads was enforced by software-based locking. The mechanisms were evaluated using both micro benchmarks as well as by adapting an open-source in-memory database system for persistent memory.

An additional component of the project dealt with using Hardware Transaction Memory (HTM) for durable persistent-memory transactions. HTM is a feature of high-end CPUs that uses processor mechanisms to ensure efficient transactional in-memory execution of concurrent threads. An additional challenge when using HTM with persistent memory is to ensure that the durable transaction ordering is consistent with the in-memory transaction ordering enforced by the HTM. Solutions based on extending SoftWrap as well as by extending the memory-controller design were developed and evaluated.  Both emulation as well as implementation on early experimental Apache Pass hardware systems made available by Intel were used for evaluations. These are the first solutions that can be implemented on existing processor hardware without changes to the processor cache hierarchy or HTM mechanisms.

The work supported the research of a graduate student for both an MS and a Ph.D. Several undergraduates were also involved in aspects of the research. There has also been considerable interest from industry in the work.

Last Modified: 12/04/2018
Modified by: Peter J Varman