Award Abstract # 0942629
Collaborative Research: CCLI (Exploratory): Introduction of Nanoelectronics Courses in Undergraduate Computer Science and Computer Engineering Curricula

NSF Org: DUE
Division Of Undergraduate Education
Recipient: UNIVERSITY OF NORTH TEXAS
Initial Amendment Date: April 29, 2010
Latest Amendment Date: April 29, 2010
Award Number: 0942629
Award Instrument: Standard Grant
Program Manager: Victor Piotrowski
vpiotrow@nsf.gov  (703)292-5141
DUE  Division Of Undergraduate Education
EDU  Directorate for STEM Education
Start Date: May 1, 2010
End Date: August 31, 2013 (Estimated)
Total Intended Award Amount: $89,999.00
Total Awarded Amount to Date: $89,999.00
Funds Obligated to Date: FY 2010 = $89,999.00
History of Investigator:
  • Saraju Mohanty (Principal Investigator)
     saraju.mohanty@unt.edu
  • Elias Kougianos (Co-Principal Investigator)
Recipient Sponsored Research Office: University of North Texas
 1112 DALLAS DR STE 4000
 DENTON
 TX  US  76205-1132
(940)565-3940
Sponsor Congressional District: 13
Primary Place of Performance: University of North Texas
 1112 DALLAS DR STE 4000
 DENTON
 TX  US  76205-1132
Primary Place of Performance
Congressional District:		 13
Unique Entity Identifier (UEI): G47WN1XZNWX9
Parent UEI:
NSF Program(s): S-STEM-Schlr Sci Tech Eng&Math,
CCLI-Type 1 (Exploratory)
Primary Program Source: 04001011DB NSF Education & Human Resource
1300XXXXDB H-1B FUND, EDU, NSF
Program Reference Code(s): 9178, SMET
Program Element Code(s): 153600, 749400
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.076

ABSTRACT

Computer Engineering (32)

This proposal develops a simulation-based project oriented curriculum to bootstrap a nanotechnology track among undergraduate engineering programs, with initial emphasis on computer science and engineering. The proposal develops three courses, five experimental modules for each of the courses, and web-based courseware for wider distribution of the materials.

The proposal investigates methodologies and tool sets for nanoscale design and integrates them into a novel engineering curriculum. It advances nanoelectronics education and provides students with the ability to perform futuristic nanodesigns. The free exchange of courseware and simulation-based education enables low-cost learning of nanotechnology compared to a traditional experimental approach. The proposal promotes discovery in nanoelectronics and nanotechnology due to advanced simulation, experiments, and design. The proposal replaces experimental-based highly-expensive nanotechnology education with simulation-based low-cost nanotechnology education.

This nanotechnology educational program contributes to building a workforce in the nanotechnology industries. The project-centered nanoelectronics courses provide a unique learning opportunity for faculty and students in computer science and engineering.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 11)
O. Garitselov, S. P. Mohanty, and E. Kougianos "A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits" IEEE Transactions on Semiconductor Manufacturing , v.25 , 2012 , p.26 10.1109/TSM.2011.2173957
O. Garitselov, S. P. Mohanty, and E. Kougianos "A Comparative Study of Metamodels for Fast and Accurate Simulation of Nano-CMOS Circuits" IEEE Transactions on Semiconductor Manufacturing (TSM) , v.25 , 2012 , p.26
S. Banerjee, J. Mathew, S. P. Mohanty, D. K. Pradhan, and M. J. Ciesielski "A Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization" Journal of Low Power Electronics (JOLPE) , v.7 , 2011 , p.471 http://dx.doi.org/10.1166/jolpe.2011.1160
S. Banerjee, J. Mathew, S. P. Mohanty, D. K. Pradhan, and M. J. Ciesielski "A Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization" Journal of Low Power Electronics (JOLPE) , v.7 , 2011 , p.471 http://dx.doi.org/10.1166/jolpe.2011.1160
S. P. Mohanty "Memristor: From Basics to Deployment" IEEE Potentials , v.32 , 2013 , p.34
S. P. Mohanty and E. Kougianos "DOE-ILP Assisted Conjugate-Gradient Optimization of High-K/Metal-Gate Nano-CMOS SRAM" IET Computers & Digital Techniques , v.6 , 2012 , p.240 10.1049/iet-cdt.2011.0166
S. P. Mohanty and E. Kougianos "DOE-ILP Assisted Conjugate-Gradient Optimization of High-?/Metal-Gate Nano-CMOS SRAM" IET Computers & Digital Techniques (CDT) , v.6 , 2012 , p.240
S. P. Mohanty, E. Kougianos, and O. Okobiah "Optimal Design of a Dual-Oxide Nano-CMOS Universal Level Converter for Multi-Vdd SoCs" Springer Analog Integrated Circuits and Signal Processing Journal , v.72 , 2012 , p.451 10.1007/s10470-012-9887-7
S. P. Mohanty, E. Kougianos, and O. Okobiah "Optimal Design of a Dual-Oxide Nano-CMOS Universal Level Converter for Multi-Vdd SoCs" Springer Analog Integrated Circuits and Signal Processing Journal , v.72 , 2012 , p.451
S. P. Mohanty, J. Singh, E. Kougianos, and D. K. Pradhan "Statistical DOE-ILP Based Power-Performance-Process (P3) Optimization ofNano-CMOS SRAM" Elsevier The VLSI Integration Journal , v.45 , 2012 , p.33 10.1016/j.vlsi.2011.07.001
S. P. Mohanty, J. Singh, E. Kougianos, and D. K. Pradhan "Statistical DOE-ILP Based Power-Performance-Process (P3) Optimization of Nano-CMOS SRAM" Elsevier The VLSI Integration Journal , v.45 , 2012 , p.33 10.1016/j.vlsi.2011.07.001
(Showing: 1 - 10 of 11)

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

The goal of the project was to investigate simulation?based project?oriented nanotechnology  teaching for multidisciplinary undergraduate engineering programs. The key outcomes of the project are the following:

  1. Client-Server model for laboratory set up and mixed-mode model of laboratory set up are two options for CAD laboratory based experiments on nanoelectronic circuits.
  2. Designers should choose Latin Hybercube Sampling (LHS) or Middle Latin Hypercube Sampling (MLHS) over Monte Carlo (MC) for statistical sampling of design space of nanoelectronic circuits.
  3. One front-end and one back-end design and simulation flow is made available using free/open-source tools for low-cost nanoelectronics circuit and system learning.
  4. Two nanoscale CMOS based SRAM design optimization flows and three RAM alternative topologies are developed for robust memory design.
  5. A 45nm datapath component library and one architecture level design flowexploration flow is available for nano-CMOS digital circuits.
  6. Automated nanoelectronic design exploration flow could be established usingMATLAB, Cadence, and ocean script.
  7. Nanoelectronic system design simulation ismade possible using Simscape for learning through illustrations.
  8. A large selection of modeling approaches and optimization algorithms areavailable for nanoelectronic circuits and systems.
  9. Syallabi for Nanoscale Mixed-Signal System Design and Low-Power Nanoelectronics courses.
  10. Lecture slides for Nanoscale Mixed-Signal System Design and Low-Power Nanoelectronics courses.

During the execution of this project, syllabi, lecture sldies, laboratory moculde of two courses: Nanoscale Mixed-Signal System Design and Low-Power Nanoelectronics could be made possible. The courses were offered under two umbrella courses Adavced Topics in VLSI Systems and Topics in VLSISystems at the University of North Texas, Denton.  The course slides are available in project website which can be used by other faculty to offer similar courses in the area of nanoelectronic circuits and systems. A book and 21 journal and conference articles published during the execution of this project.

Several presentations were given in international conferences to disseminate the research and education outcomes. PI gave a webinar organized by Semiconductor Research Corportation (SRC), Texas Analog Center for Excellence (TxACE), which was globally broadcasted.  PI made presentation in Estonia at the Energy Efficient community workshop 2013 organized by UNTand University of Tartu for international collaboration. Students were trained and given opportunity to present research at international conferences. Students got wider exposure in nanoelectronic circuits and systems. Students got trained in MATLAB/Simulink/Simscape/CAD tools in nanoelectronic circuits and systems.

 

 

 


Last Modified: 09/04/2013
Modified by: Saraju P Mohanty

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