NSF Org:	ECCS Division of Electrical, Communications and Cyber Systems
Recipient:	MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Initial Amendment Date:	September 19, 2002
Latest Amendment Date:	November 14, 2006
Award Number:	0202487
Award Instrument:	Continuing Grant
Program Manager:	Paul Werbos ECCS  Division of Electrical, Communications and Cyber Systems ENG  Directorate for Engineering
Start Date:	October 1, 2002
End Date:	September 30, 2007 (Estimated)
Total Intended Award Amount:	$0.00
Total Awarded Amount to Date:	$470,993.00
Funds Obligated to Date:	FY 2002 = $156,999.00 FY 2003 = $156,999.00 FY 2004 = $156,995.00
History of Investigator:	Cardinal Warde (Principal Investigator) warde@mit.edu Clifton Fonstad (Co-Principal Investigator)
Recipient Sponsored Research Office:	Massachusetts Institute of Technology 77 MASSACHUSETTS AVE CAMBRIDGE MA  US  02139-4301 (617)253-1000
Sponsor Congressional District:	07
Primary Place of Performance:	Massachusetts Institute of Technology 77 MASSACHUSETTS AVE CAMBRIDGE MA  US  02139-4301
Primary Place of Performance Congressional District:	07
Unique Entity Identifier (UEI):	E2NYLCDML6V1
Parent UEI:	E2NYLCDML6V1
NSF Program(s):	CONTROL, NETWORKS, & COMP INTE, INTEGRATIVE SYSTEMS
Primary Program Source:	app-0102  app-0103  app-0104
Program Reference Code(s):	0000, OTHR
Program Element Code(s):	151800, 151900
Award Agency Code:	4900
Fund Agency Code:	4900
Assistance Listing Number(s):	47.041

ABSTRACT

The objective of this research program is to develop algorithms and architectures, and fabricate and demonstrate a rugged, compact, modular, versatile, opt electronic, integrated-circuit (OEIC) neural network and fuzzy logic coprocessor system that would work in conjunction with the standard PC microprocessor. This OEIC co-processor will perform sophisticated parallel and/or fuzzy processing operations more efficiently than the standard PC microprocessor. The proposed OElC co-processor will be about the size of a CD-ROM drive, and thus would fit easily inside the case of a conventional personal computer. Another important goal of the program is that this compact OEIC co-processor be amenable to mass manufacturing.


To demonstrate the feasibility of the co-processor, the proposed hardware development tasks include: (I) design, fabrication and characterization of novel 2-D arrays of GaAs-SOS (silicon-on sapphire) OEIC cascadable smart pixels with a detector, integrated-circuit logic and a light source in each pixel (resonant cavity light-emitting diodes (RCLEDs) in the first two years of the program, and vertical-cavity surface-emitting lasers (VCSELs) replacing the RCLEDs in the third year), (2) design, fabrication and characterization of novel reconfigurable optical interconnection elements based on arrays of Bragg-holographic phase gratings, (3) aligning (with the help of a mask aligner) and gluing all the components of the co-processor (OEICs. interconnection elements, and output photodetector array) together into a rugged, compact, modular multi-layer sandwich configuration so as to permanently solve any micro-optics alignment problems, and (4) characterizing the resulting high-speed, multilayer optoelectronic co-processor. The early focus of the program will be on neural network configurations. So in addition to the above-mentioned fabrication tasks, the PI will also carry' out the following theoretical, modeling and simulation tasks: (a) develop algorithms, especially those suitable for programmable nearest-neighbor interconnections (e.g. pulse-coupled networks) to solve a large class of multi-dimensional information processing problems, and (b) explore the application of these novel co-processors to three different types of problems: (i) associative-memory-based pattern recognition, (ii) medical image segmentation and (iii) fusion of a set of low-contrast spectro-polarimetric infrared images into a single high-contrast image.

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