| NSF Org: |
CNS Division Of Computer and Network Systems |
| Recipient: |
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| Initial Amendment Date: | June 7, 2006 |
| Latest Amendment Date: | May 15, 2008 |
| Award Number: | 0551401 |
| Award Instrument: | Continuing Grant |
| Program Manager: |
Chitaranjan Das
CNS Division Of Computer and Network Systems CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | June 1, 2006 |
| End Date: | May 31, 2010 (Estimated) |
| Total Intended Award Amount: | $401,918.00 |
| Total Awarded Amount to Date: | $401,918.00 |
| Funds Obligated to Date: |
FY 2007 = $9,778.00 FY 2008 = $10,266.00 |
| History of Investigator: |
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| Recipient Sponsored Research Office: |
21 N PARK ST STE 6301 MADISON WI US 53715-1218 (608)262-3822 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
21 N PARK ST STE 6301 MADISON WI US 53715-1218 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): | CCRI-CISE Cmnty Rsrch Infrstrc |
| Primary Program Source: |
app-0107 01000809DB NSF RESEARCH & RELATED ACTIVIT |
| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Review Analysis
Program: NSF 04-588 CISE Computing Research Infrastructure
Title: CRI A MASSIV Cluster for Designing Chip Multiprocessors
Proposal: CNS 0551401
PI: Hill, Mark D.
Institution: University of Wisconsin-Madison
Researchers at the University of Wisconsin, Madison will acquire a computing cluster infrastructure, distinguished by large memory and storage capacity, that will facilitate research on designs for multiple processors on a single. The compute cluster will enable the group to research innovative new designs through simulation and evaluation of designs that are tested against large, future workloads. Research will look at innovations such as log-based transactional memory to ease multithreaded programming, using hardware to aid multithreaded debugging, leveraging token coherence for aggressive CMP memory hierarchies, using compression to enlarge on-CMP caches and reduce off-CMP bandwidth requirements, exploiting on-CMP transmission lines for novel cache architectures, facilitating speculative parallelization and multithreading, handling increasing memory latencies, parallelizing the execution of system-intensive workloads on novel CMP micro-architectures, minimizing the performance impacts of robust, reliable software, and exploring new ways such as coherence decoupling to address cache coherence. Broader impacts of this project include training, industry partnerships, and sharing the evaluation infrastructure and simulated workloads with other research groups.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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