Award Abstract # 1619261
STARSS: Small: GC@Scale: Synthesis, optimization, and implementation of Garbled Circuits for Scalable Privacy-Preserving Computing

NSF Org: CNS
Division Of Computer and Network Systems
Recipient: UNIVERSITY OF CALIFORNIA, SAN DIEGO
Initial Amendment Date: August 18, 2016
Latest Amendment Date: August 18, 2016
Award Number: 1619261
Award Instrument: Standard Grant
Program Manager: Daniela Oliveira
doliveir@nsf.gov
 (703)292-0000
CNS
 Division Of Computer and Network Systems
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: October 1, 2016
End Date: September 30, 2020 (Estimated)
Total Intended Award Amount: $298,231.00
Total Awarded Amount to Date: $298,231.00
Funds Obligated to Date: FY 2016 = $298,231.00
History of Investigator:
  • Farinaz Koushanfar (Principal Investigator)
    farinaz@ucsd.edu
Recipient Sponsored Research Office: University of California-San Diego
9500 GILMAN DR
LA JOLLA
CA  US  92093-0021
(858)534-4896
Sponsor Congressional District: 50
Primary Place of Performance: University of California-San Diego
9500 Gilman Dr
La Jolla
CA  US  92093-0407
Primary Place of Performance
Congressional District:
50
Unique Entity Identifier (UEI): UYTTZT6G9DT1
Parent UEI:
NSF Program(s): Secure &Trustworthy Cyberspace
Primary Program Source: 01001617DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 7434, 7923, 8225, 9102, 021Z
Program Element Code(s): 806000
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

Computing on sensitive data is a standing challenge central to several modern-world applications. Secure Function Evaluation (SFE) allows mistrusting parties to jointly compute an arbitrary function on their private inputs without revealing anything but the result. The GC@Scale project focuses on novel scalable methods for addressing SFE, which directly translate to stronger cryptography and security for myriads of tasks with sensitive data. The applications are wide reaching and include privacy-preserving processing of medical, genome, and biometric data, as well as personal, government, and industrial cloud computing. The project includes an ambitious educational program that targets both undergraduate/ graduate students, and also addresses issues related to outreach.

The concept of SFE using Garbled Circuits (GC) was introduced by Yao. Despite a decade of research in GC implementation and several key progresses, scalability of the available methods has been hampered by the circuit representation as a directed acyclic graph, and software-level local logic optimizations. GC@Scale leverages PI's recent work, which has changed the SFE landscape by viewing GC generation as an atypical sequential logic synthesis. The project plans to advance the understanding and enable expanded exploration of SFE methodologies, while simultaneously enriching the theory, practice, and tools for logic design, synthesis, mapping and optimization. The proposed plan includes: (i) design and FPGA implementation of an efficient general purpose Garbled Processor for secure computation; (ii) Creating the challenging application-specific GC matching and search engines with a higher than linear complexity. (iii) Devising new custom SFE engines for Machine Learning tasks.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 19)
Bita Darvish Rouhani, Siam Umar Hussain, Kristin E. Lauter, Farinaz Koushanfar "ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs" ACM Transactions on Reconfigurable Technologies and Systems , v.11 , 2018 , p.1 10.1145/3242899
Bita Darvish Rouhani, Siam Umar Hussain, Kristin E. Lauter, Farinaz Koushanfar "ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs." ACM Transactions on Reconfigurable Technologies and Systems , v.11 , 2018
Ebrahim M. Songhori, M. Sadegh Riazi, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar "ARM2GC: Succinct Garbled Processor for Secure Computation" Design Automation Conference (DAC) , 2019 , p.1 10.1145/3316781.3317777
Ebrahim M. Songhori, M. Sadegh Riazi, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar "ARM2GC: Succinct Garbled Processor for Secure Computation." Design Automation Conference (DAC) , 2019
Mohsen Imani, Yeseong Kim, M. Sadegh Riazi, John Messerly, Patric Liu, Farinaz Koushanfar, Tajana Rosing "A Framework for Collaborative Learning in Secure High-Dimensional Space" IEEE 12th International Conference on Cloud Computing (CLOUD) , 2019
M. Sadegh Riazi, Bita Darvish Rouhani, Farinaz Koushanfar "Deep Learning on Private Data" IEEE S&P , 2019
M. Sadegh Riazi, Bita Darvish Rouhani, Farinaz Koushanfar "Deep Learning on Private Data" IEEE S&P , 2019
M. Sadegh Riazi, Christian Weinert, Oleksandr Tkachenko, Ebrahim M. Songhori, Thomas Schneider, Farinaz Koushanfar "Chameleon: A Hybrid Secure Computation Framework for Machine Learning Applications" AsiaCCS , 2018 10.1145/3196494.3196522
M. Sadegh Riazi, Christian Weinert, Oleksandr Tkachenko, Ebrahim M. Songhori, Thomas Schneider, Farinaz Koushanfar "Chameleon: A Hybrid Secure Computation Framework for Machine Learning Applications" AsiaCCS , 2018
M. Sadegh Riazi, Mohammad Samragh, Farinaz Koushanfar "CAMsure: Secure Content-Addressable Memory for Approximate Search" ACM Transactions on Embedded Computing Systems (TECS) , v.6 , 2017 10.1145/3126547
M. Sadegh Riazi, Mojan Javaheripi, Siam U. Hussain, Farinaz Koushanfar "MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation" Hardware-Oriented Security and Trust (HOST) , 2019 10.1109/HST.2019.8740831
(Showing: 1 - 10 of 19)

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

Security and privacy are paramount concerns in development and employment of technologies and applications. The results of this project are of interest to fabless semiconductor companies, US government agencies and university researchers worldwide. Benefits to the society include secure and trustworthy electronics for healthcare, defense, finance, transportation, automotive and other applications. The results will be disseminated in technical events, via Trust-Hub website and in open-source format.

This project is impacting the field in myriads of ways, starting from the development of basic knowledge, theory, research, all the way to publications, open-source software, and open-source teaching material that all contribute to the healthy and constant progress of the field.

In particular, the methods for efficient machine learning are based on fundamental newly developed methodologies that integrate a combination of hardware characterization/computer engineering, which aim to significantly improve performance.

Our research on hardware acceleration of secure machine learning has accelerated the privacy-preserving inference by 3 orders of magnitude. Data privacy is one of the most discussed and debated topics in the past few years. Still ensuring complete privacy of the user data had been considered close to impossible. Our work brings the complexity of this task within practical limits and shows the promise to be adopted in the industry within few years. 

The project has made a significant mark in the development of the field, by presenting the following results in the last year of the review period:

* MPCircuits, the first scalable multi-party security platform.

* ARM2GC, a new compiler that translates the commands from a high level (ARM c++ compiled code) to GC framework.

* Chameleon, a new hybrid protocol for privacy-preserving deep learning which reported the most efficient results to date (on the day of publication) in the field.

* FASE, a general-purpose FPGA framework for acceleration of the GC.

The material developed in this project is being used in PI's graduate hardware and embedded security course in UCSD. The PI is teaching an undergraduate course in FPGA Verilog. The hands-on project for that course draws upon the material devised in this project and is about bitcoin hashing on FPGA. 

The PI has actively helped with organizing workshops and conferences or contributed tutorials and invited sessions to these event. The tools and methodology devised in this project are used and cited by other researchers in the field (e.g., the Chamelon paper alone is 125 times cited) and by myriads of researchers and practitioner who are interested in privacy-preserving applications. 


Last Modified: 11/15/2021
Modified by: Farinaz Koushanfar

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