
NSF Org: |
CCF Division of Computing and Communication Foundations |
Recipient: |
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Initial Amendment Date: | July 30, 2015 |
Latest Amendment Date: | July 30, 2015 |
Award Number: | 1535897 |
Award Instrument: | Standard Grant |
Program Manager: |
Tracy Kimbrel
CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
Start Date: | September 1, 2015 |
End Date: | August 31, 2019 (Estimated) |
Total Intended Award Amount: | $200,000.00 |
Total Awarded Amount to Date: | $200,000.00 |
Funds Obligated to Date: |
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History of Investigator: |
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Recipient Sponsored Research Office: |
341 PINE TREE RD ITHACA NY US 14850-2820 (607)255-5014 |
Sponsor Congressional District: |
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Primary Place of Performance: |
331 Rhodes Hall Ithaca NY US 14853-3801 |
Primary Place of
Performance Congressional District: |
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Unique Entity Identifier (UEI): |
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Parent UEI: |
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NSF Program(s): | Algorithms in the Field |
Primary Program Source: |
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Program Reference Code(s): |
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Program Element Code(s): |
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Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.070 |
ABSTRACT
Discrete programming (DP) deals with optimization problems involving variables that range over a discrete (e.g., integer-valued) solution space. DP is an important tool in a variety of practical applications including digital communications, operations research, power grid optimization, and computer vision. While discrete programs are typically solved offline by sophisticated software using powerful computers, DP has recently emerged as an important tool in applications requiring real-time processing in embedded systems with stringent area, cost, and power constraints. Since existing DP solvers entail prohibitive complexity and power consumption when implemented on existing embedded hardware, novel algorithms and hardware architectures are necessary to unlock the potential of DP in real-time applications. This project fuses optimization theory, numerical methods, and circuit design to develop fast algorithms and suitable hardware architectures for real-time DP in embedded systems. Besides a thorough theoretical analysis of the proposed methods, the project includes extensive software and hardware benchmarking to reveal the efficacy of real-time DP in practice. To bridge the ever-growing gap between recent advances in numerical optimization and hardware design, the project also includes the development of undergraduate and graduate courses that build upon the vertically-integrated research approach of this project, in addition to offering summer research internships (REUs) to introduce young scientists to the field of discrete programming.
The project develops a set of computationally efficient and hardware-aware algorithms and corresponding dedicated very-large scale integration (VLSI) architectures that enable DP for real-time embedded systems. The proposed DP algorithms rely on a variety of algorithmic transformations, ranging from semidefinite and infinity-norm-based relaxations to exact variable-splitting methods and non-convex approximations. These disparate approaches offer a wide range of tradeoffs between solution quality and hardware implementation complexity. The project studies these fundamental tradeoffs, as well as the effects of finite-precision arithmetic in VLSI, from both a theoretical and practical perspective. To carry out this investigation, three dedicated VLSI architectures will be developed that exploit the inherent parallelism of the proposed algorithms. These architectures target (i) data detection in multi-antenna (MIMO) wireless systems that is the key bottleneck in next-generation communication systems, (ii) signal recovery problems in hyperspectral imaging, and (iii) phase retrieval problems from x-ray crystallography. By investigating the domain-specific performance and complexity of various numerical solvers in a variety of conditions and hardware configurations, the project will reveal the efficacy and limits of DP for a broad range of real-time applications beyond the ones studied in this project.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
The goals of this project are in the development of new algorithms, analysis of theoretical properties, and implementation of hardware prototypes that compute approximate solutions to high-dimensional discrete programs. Before this project, it was commonly believed that approximate or relaxation-based methods for discrete programming exhibit prohibitive complexity, which prevents their deployment in practical systems or achieve poor solution quality. However, the reference algorithms and hardware designs developed in this project have demonstrated that relatively large discrete programs can be solved at high throughput, low area, and low power, while achieving best-in-class solution accuracy. Specifically, the PIs have developed three distinct algorithm frameworks for approximately solving a wide range of discrete program classes: (i) triangular approximate semidefinite relaxation (TASER), (ii) biconvex relaxation (BCR), and (iii) l-infinity-norm relaxation. In addition, theoretical results addressing convergence properties and solution quality have been devised. To demonstrate the efficacy of these algorithm frameworks in real-world applications, the PIs have developed reference very-large scale integration (VLSI) designs for next-generation wireless communication systems, including near-maximum-likelihood data detection, joint channel estimation and data detection, and precoding for low-resolution multi-antenna transmitters. These reference hardware designs achieve best-in-class throughput, area, and power, while surpassing the performance of existing algorithms in wireless systems. Furthermore, the algorithm frameworks developed in this project have been applied to a range of applications in other fields, such as imaging, signal processing, computer vision, and machine learning.
Broader Impacts
The PIs have been actively collaborating with industry partners in the areas of field-programmable gate arrays and wireless network infrastructure. In the ever-growing area of wireless systems, the achieved results have the potential to enable higher data rates or more devices (or sensors) connected to the base stations. In addition, some of the developed methods enables base-station designs that consume orders of magnitude lower power than traditional solutions. On the mobile handheld side, the developed methods enable the solution to combinatorial data detection problems at significantly lower power and with fewer errors; this has an immediate impact on a society that becomes increasingly interested in energy efficiency computing. The achieved results have also potential benefit for people in areas of underserved communication infrastructure as they enable reliable communication over longer distances.
The PIs have integrated undergraduate students directly into the research of this project and have included results in new communications and optimization courses at Cornell University and University of Maryland. In addition, the project outreach activities culminated in a week-long research activity for underrepresented minority (URM) high-school students under Cornell?s CATALYST Academy, in which the students were developing an acoustic wireless communication system.
Last Modified: 01/10/2020
Modified by: Christoph Studer
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