| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
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| Initial Amendment Date: | July 28, 2014 |
| Latest Amendment Date: | July 28, 2014 |
| Award Number: | 1439085 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Anindya Banerjee
abanerje@nsf.gov (703)292-7885 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | August 1, 2014 |
| End Date: | July 31, 2017 (Estimated) |
| Total Intended Award Amount: | $300,000.00 |
| Total Awarded Amount to Date: | $300,000.00 |
| Funds Obligated to Date: |
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| History of Investigator: |
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| Recipient Sponsored Research Office: |
1 NASSAU HALL PRINCETON NJ US 08544-2001 (609)258-3090 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
87 Prospect Avenue Princeton NJ US 08544-2020 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): | Exploiting Parallel&Scalabilty |
| Primary Program Source: |
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| Program Reference Code(s): | |
| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Unable to increase computer processor peformance growth at the historic rate, the microprocessor industry has shifted to bundling more processor cores in each computer. While additional processor cores puts more processing power in each computer, the burden of making use of this power shifts to the programmer. To make matters worse, the cores in each computer are not all the same and each computer model may have a different number and mix of cores. Software optimized for one computer may perform poorly for another, and having programmers optimize for each computer model is not practical. This project intends to overcome these problems by changing the way programmers write code for these systems and having the computer optimize the software for its specific configuration. The project will study ways to convey the richer set of information necessary to help computers best optimize the software running upon it. This project has the potential to fundamentally alter how programmers develop software for modern architectures, relieving them of the arduous task of optimizing their code for different systems. Users of any software---from computational scientists to home desktop users---would experience an increase in performance and faster deployment of new applications.
The proposed software interface must represent code in a way that is automatically analyzable and highly amenable to automatic code transformations at runtime. The project will explore many designs, including explicitly encoding register dependences in Single Static Assignment (SSA) form, statically determining and encoding memory dependency information into instructions, and using an expressive code layout scheme to make runtime analysis and optimization more efficient. In concert with this design space exploration, various runtime optimizations will be developed which will customize the software execution for the specific computer while also optimizing for dynamically changing user desires such as execution speed and energy consumption. The synergistic design of the software interface and runtime optimizations will allow determination of the optimal set of information to include in the interface. This project also aims to create tools for developers (compiler, assembler, and architectural simulator) to enable others to use and evaluate it.
The PI will keep building on his past successes in fostering diversity and educational outreach efforts. He will host several undergraduate student researchers each year, teaming them with graduate student mentors. He will also continue to incorporate current research results into undergraduate and graduate courses.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
With the near universal adoption of multi-core and many-core architectures, parallel performance portability and dynamic adaptability are more important than ever before. To deliver portable performance on current and future architectures, even in the presence of dynamically varying execution environments, this project pursued three different, but complementary, avenues of research: a new and more expressive ISA design, a micro-architectural optimizer for dynamic parallelization, and supporting technology to utilize the new ISA and optimizer. Over the life of the project, the project team designed and developed a number of novel supporting technologies necessary for next-generation multi-core and many-core architecture. These technologies have already influenced other researchers and are in various stages of dissemination by the project team and others to encourage wider use.
This research has contributed to the education and development of many graduate students, many of whom have already earned a Ph.D. and joined the workforce. This project also contributed material to courses aimed at educating graduate and undergraduate students about multicore processors, thread extraction, dynamic compilation, and parallelism in general. Hundreds of elementary school students have been inspired by demonstrations given by the PI and others on the project team. Students touched by this project are making significant contributions at universities and technology companies in the United States.
Last Modified: 08/20/2017
Modified by: David I August
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