
NSF Org: |
CCF Division of Computing and Communication Foundations |
Recipient: |
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Initial Amendment Date: | July 9, 2014 |
Latest Amendment Date: | May 6, 2015 |
Award Number: | 1422489 |
Award Instrument: | Standard Grant |
Program Manager: |
Sankar Basu
sabasu@nsf.gov (703)292-7843 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
Start Date: | July 15, 2014 |
End Date: | June 30, 2018 (Estimated) |
Total Intended Award Amount: | $449,999.00 |
Total Awarded Amount to Date: | $457,999.00 |
Funds Obligated to Date: |
FY 2015 = $8,000.00 |
History of Investigator: |
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Recipient Sponsored Research Office: |
633 CLARK ST EVANSTON IL US 60208-0001 (312)503-7955 |
Sponsor Congressional District: |
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Primary Place of Performance: |
2145 Sheridan Road Evanston IL US 60208-0834 |
Primary Place of
Performance Congressional District: |
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Unique Entity Identifier (UEI): |
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Parent UEI: |
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NSF Program(s): | Software & Hardware Foundation |
Primary Program Source: |
01001516DB NSF RESEARCH & RELATED ACTIVIT |
Program Reference Code(s): |
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Program Element Code(s): |
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Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.070 |
ABSTRACT
Power consumed by integrated circuits (ICs) converts to heat and dissipates through the material of the IC and the surrounding packaging. Heat dissipation from the interior of an IC to the ambient becomes highly constrained when power hungry high performance chips are stacked vertically to create 3D ICs. Pockets of accumulated heat with poor heat conduction paths to the ambient is then trapped in between stacked IC layers. As a result, overheating within ICs threaten the safety and performance of future computing systems that rely on this important new IC design methodology. This project will develop a new thermal sensor design that is especially well suited to be integrated into 3D ICs during semiconductor processing steps. It is smaller by design, i.e., an arbitrarily large number of sensors can monitor an unprecedented part of the IC, and they do not consume additional power. This will impact the sustainability and computational power of future computing systems by enabling them to operate at maximal frequencies without the need for costly active cooling solutions. They also affect the pricing of the chip products and therefore have a direct impact on the industry and economy. The PIs will continue to train graduate and undergraduate students in the basic research that underlies creative technological developments and actively promote science and technology in outreach events to the community. One of the PIs will also leverage her membership in the Diversity Committee at her institution to attract underrepresented minority graduate student applicants.
The project involves a new paradigm for design of thermal sensors using Thin Film Bimetallic Thermocouples (TFBTs), which senses temperature according to an intrinsic material property that is independent of process variation and thermal conditions of the environment. Since TFBTs are passive, they do not consume power or dissipate heat during sensing. Significant challenges remain in better understanding and modeling of the materials as well as the integration of the TFBTs into 3D ICs. The project will study the basic science of these thermocouple metals as a function of layer thickness, since thin film Seebeck coefficients are known to differ significantly from bulk. Particularly, experiments will be undertaken to investigate the dependence of the Seebeck coefficient on film thickness and on the choice of various candidate metals for thermocouples. Samples using integrated resistive heater elements on semiconductor substrates will simulate hot spots underneath arrays of bimetallic thermocouples, generating thermal maps with high spatial resolution. Design optimizations for effective integration into 3D ICs will be developed. Novel thermal management schemes that can make use of the resulting fine-grain, robust, and low cost sensor array will be developed
and evaluated.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
Users of smart phones and tablets are familiar with overheating and the resulting slow response of their devices. They have been familiar for an even longer time with the loud humming of cooling fans in high-end desktop and server environments. Understanding the thermal response and managing it with the least impact on the performance of these systems is one of the primary issues in modern computing. Our project aimed at developing new temperature sensors at nanoscale that can be embedded into integrated circuits in large quantities with a practical manufacturing process. Their ability to generate high resolution thermal maps of a circuit's interior creates new opportunities for on-demand and on-the-point interventions and design optimizations. Thereby, we can avoid a single hotspot surrounding a small number of logic gates putting an entire multi-core processor chip in jeopardy.
Specifically, this project developed optimized fabrication flows (material choices, dimensions, etc.) for photolithographically integrated bimetallic thin film thermocouples. Circuit and system level methodologies for allocating these sensors within large chips and interfacing them with the existing inftrastructures (dynamic thermal management units in processors) have also been developed for a complete end-to-end solution. The resulting sensor infrastructure occupies orders of magnitude smaller silicon area (majority of the structure uses metals placed in the interconnect layers as opposed to transistors occupying the silicon layer), provides complete robustness against process variations, and requires orders of magnitude less power consumption for its own operation, since it is mainly built from passive elements.
Students trained as part of this grant have been exposed to a unique stack of activities ranging from clean room fabrication to 3D IC modeling, to power and thermal simulations of entire microprocessors at the instruction level.
Last Modified: 07/13/2018
Modified by: Seda Memik
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