| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
|
| Initial Amendment Date: | July 9, 2014 |
| Latest Amendment Date: | July 9, 2014 |
| Award Number: | 1421823 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Yuanyuan Yang
CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | August 1, 2014 |
| End Date: | July 31, 2019 (Estimated) |
| Total Intended Award Amount: | $479,998.00 |
| Total Awarded Amount to Date: | $479,998.00 |
| Funds Obligated to Date: |
|
| History of Investigator: |
|
| Recipient Sponsored Research Office: |
75 LOWER COLLEGE RD RM 103 KINGSTON RI US 02881-1974 (401)874-2635 |
| Sponsor Congressional District: |
|
| Primary Place of Performance: |
70 Lower College Rd Kingston RI US 02881-1967 |
| Primary Place of
Performance Congressional District: |
|
| Unique Entity Identifier (UEI): |
|
| Parent UEI: |
|
| NSF Program(s): | Software & Hardware Foundation |
| Primary Program Source: |
|
| Program Reference Code(s): |
|
| Program Element Code(s): |
|
| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Big data applications demand high speed, reliable, and energy
efficient data storage systems. Traditional storage architectures have
fundamental limitations because of legacy systems that have centered
on spinning hard disk drives. With rapid advances in nonvolatile
memory technologies such as NAND-gate flash, phase change memory, Memristor, and
magnetic RAM, a great opportunity arises for revolutionizing storage
architectures. The objective of this research is to start a paradigm
shift in storage architecture to meet the increasing demand of big
data applications. It is envisioned that future storage systems will
have machine intelligence that learns, analyzes, predicts, and
controls the system at runtime dynamically. A novel accelerator
architecture is introduced with machine intelligence to enable high
speed processing of storage data operations that are critical to high
performance computing in general and big data computing in particular.
The newly introduced I/O accelerator, residing either in a
many-core CPU chip or on a storage controller board, enables
sufficiently accurate predictions for effective optimization of
storage I/Os. With new architecture features, the proposed I/O
accelerator can carry out complicated I/O tasks in the speed
comparable to the emerging nonvolatile memories, which is critical to
I/O performance because it no longer operates in milliseconds as
spinning disks do. The project will explore and implement the I/O
accelerator that can effectively deal with the complexity and high
dimensionality of factors related to diverse storage technologies, a
large variation of application workloads, different
reliability/availability requirements, and power consumptions of
various storage components. The result is a new heterogeneous storage
architecture that is optimized for future computing infrastructure.
With the accelerator as an enabler, comprehensive methodology will be
investigated that proactively learns system behavior to anticipate
long-term trends and to respond quickly to fast changing I/O events.
The new architecture is believed to be the first of the kind providing
dynamic optimizations by means of 1) intelligent data placements and
replacements across heterogeneous devices, 2) optimal resource
allocation and provisioning to applications' workloads, 3) effective
data deduplication based on content locality, and 4) smart policy
decision on data protection and recovery adaptive to different data
types. Furthermore, the new accelerator enables fast in-situ data
analytics in active storage systems.
This research project is expected to have the following broader impacts:
1) In today's cloud computing and big data
applications, servers generate a large amount of I/Os that can take
full advantage of the new storage architecture. 2) The new accelerator
can be incorporated into many core CPUs as a specialized core for
future heterogeneous processors. 3) The new storage architecture will
speed up the adoption of emerging storage class memories. 4) The new
methodology will stimulate more research in applying machine learning
to storage systems. 5) The new CPU-and-data centric Computer Engineering curriculum will train
both graduate and undergraduate students for real world needs. 6) The
outreach program will continue the success stories of prior NSF
projects to help the economic development of the state of Rhode Island and the
nation.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Note:
When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external
site maintained by the publisher. Some full text articles may not yet be available without a
charge during the embargo (administrative interval).
Some links on this page may take you to non-federal websites. Their policies may differ from
this site.
PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
Big data applications demand high speed, reliable, and energy efficient data storage systems. Traditional storage architectures have fundamental limitations because of legacy systems that have centered on spinning hard disk drives. With rapid advances in nonvolatile memories such as NAND-gate flash, phase change memory, Memristor, and magnetic RAM, a great opportunity exists for revolutionizing storage architectures. The objective of this research is to meet the increasing demand of big data applications. Novel accelerator architecture has been introduced with machine intelligence to enable high speed processing of storage data operations that are critical to high performance computing in general.
As results of this research project, we have developed 1) a reconfigurable real-time high performance SVM classification architecture that provides an average speed-up as high as 53x, and energy savings reaching an estimated minimum of 12x; 2) Registor: a platform for regex processing in storage; 3) HODS: Hardware Object Deserialization inside SSD Storage improving the overall performance at application level by 10% to a factor of 4.3; 4) WARCIP: write amplification reduction by clustering I/O pages; And 5) CISC: coordinating intelligent SSD and CPU to speedup graph processing.
We expect that all or some of these new architectures will likely to have broader impact in computer industry. Four PhD students have graduated with confirmed degree under this project. These PhD graduates are now working in computer industry and government organizations.
Last Modified: 08/14/2019
Modified by: Qing Yang
Please report errors in award information by writing to: awardsearch@nsf.gov.
