NSF Org:	CCF Division of Computing and Communication Foundations
Recipient:	THE LELAND STANFORD JUNIOR UNIVERSITY
Initial Amendment Date:	September 10, 2013
Latest Amendment Date:	September 10, 2013
Award Number:	1337375
Award Instrument:	Standard Grant
Program Manager:	Tao Li CCF  Division of Computing and Communication Foundations CSE  Directorate for Computer and Information Science and Engineering
Start Date:	September 15, 2013
End Date:	August 31, 2015 (Estimated)
Total Intended Award Amount:	$260,000.00
Total Awarded Amount to Date:	$260,000.00
Funds Obligated to Date:	FY 2013 = $260,000.00
History of Investigator:	Oyekunle Olukotun (Principal Investigator) kunle@stanford.edu Christoforos Kozyrakis (Co-Principal Investigator)
Recipient Sponsored Research Office:	Stanford University 450 JANE STANFORD WAY STANFORD CA  US  94305-2004 (650)723-2300
Sponsor Congressional District:	16
Primary Place of Performance:	Stanford University 353 Serra Mall Stanford CA  US  94305-9025
Primary Place of Performance Congressional District:	16
Unique Entity Identifier (UEI):	HJD6G4D6TJY5
Parent UEI:
NSF Program(s):	Exploiting Parallel&Scalabilty
Primary Program Source:	01001314DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s):
Program Element Code(s):	828300
Award Agency Code:	4900
Fund Agency Code:	4900
Assistance Listing Number(s):	47.070

ABSTRACT

Information technology is now a major catalyst for innovation across all aspects of human endeavor. Hence, it is vital to maintain the exponential performance growth of computing devices that has been the key enabler for information technology advances for more than four decades. In the past, semiconductor technology provided us with increasing transistor densities and decreasing power supplies, allowing us to improve performance without increasing energy consumption. However, the lack of power supply scaling in current and future technologies has made all computing systems energy limited. Improving energy efficiency is a defining challenge and the prerequisite to increasing the capabilities of all computing systems, from smartphones to warehouse-scale data-centers.
 
The goal of this project is to enable cost-effective customized computing by bridging the gap between high-level application development and the design of specialized hardware for energy efficient computing. Specialization is the prevailing approach for energy efficient computing, as customized units can eliminate the energy overheads of general-purpose cores. However, the complexity of designing and managing customized hardware is currently limiting the benefits from specialization to high-volume, slowly evolving applications. We will create domain specific synthesis tools that, given an application written in an easy-to-use, domain-specific programming language, will generate domain or application specific hardware: compute units and memory systems. The core of our approach to domain specific synthesis is a combination of domain specific languages to capture high-level application information, domain-specific optimization, parallelism and locality optimization, and hardware generation from parallelism and locality patterns.

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

Intellectual Merit

In recent years, due to the slowing of Moore's Law and power constraints, the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising as they offer significant performance and power improvements compared to CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software development languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient.

Under this project we have developed high-level software environments for generating high-performance FPGA designs. Functional languages with parallel patterns are a good fit for hardware generation because they both provide high-level abstractions for programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages like C++. We have  identified two key optimizations that are important for translating parallel patterns into efficient hardware: tiling and metapipelining (hierarchical pipelining). We have developed a general representation of tiled parallel patterns, and rules for automatically tiling patterns and generating metapipelines. We have demonstrated  that these optimizations result in speedups up to 40 times on a set of benchmarks from the data analytics domain.

 

Broader Impacts

This project has provided for the training and professional development of three graduate students. One of these students is an underrepresented minority.

 

 

 

 

 

Last Modified: 12/11/2015
Modified by: Oyekunle A Olukotun

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