| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
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| Initial Amendment Date: | July 31, 2013 |
| Latest Amendment Date: | June 16, 2015 |
| Award Number: | 1318826 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Yuanyuan Yang
CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | September 1, 2013 |
| End Date: | August 31, 2018 (Estimated) |
| Total Intended Award Amount: | $499,948.00 |
| Total Awarded Amount to Date: | $531,948.00 |
| Funds Obligated to Date: |
FY 2014 = $16,000.00 FY 2015 = $16,000.00 |
| History of Investigator: |
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| Recipient Sponsored Research Office: |
1000 OLD MAIN HL LOGAN UT US 84322-1000 (435)797-1226 |
| Sponsor Congressional District: |
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| Primary Place of Performance: |
4120 Old Main Hill Logan UT US 84322-4120 |
| Primary Place of
Performance Congressional District: |
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| Unique Entity Identifier (UEI): |
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| Parent UEI: |
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| NSF Program(s): |
Software & Hardware Foundation, COMPUTER ARCHITECTURE, EPSCoR Co-Funding |
| Primary Program Source: |
01001415DB NSF RESEARCH & RELATED ACTIVIT 01001516DB NSF RESEARCH & RELATED ACTIVIT |
| Program Reference Code(s): |
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| Program Element Code(s): |
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| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
Rapid technology scaling has fueled an unprecedented growth in the semiconductor
industry, transforming the face of modern society. Commodity systems have
undergone a sea change from the uniprocessor era of past decades to the current
many-core era. With numerous on-chip processing cores, the communication fabric
in many-core systems becomes a critical design component. Network-on-Chip (NoC)
architectures are widely regarded as the most promising design for the
communication platform for many-core systems, primarily due to their
scalability. Many-core systems such as Intel 80-core and Tilera have already
used NoCs as the backbone of communication between their on-chip processors. To
maintain fault-free execution in these many-core systems, it is imperative to
ensure sustained lifetime in both NoCs and processing cores. This research
embarks on boosting sustainability in NoC architectures through a proactive
design paradigm.
Using a cross-layer collaborative venture, spanning from the device layer to the
architecture layer, this project establishes a transformative framework to
design sustainable NoC architectures. Existing techniques for NoCs tackle the
sustainability design challenge in a reactive way by triggering corrective
mechanisms after a component failure. The investigators explore an orthogonal
proactive strategy, recognizing the need for device level aging awareness during
the entire life span of an NoC. This project demonstrates that sustainability
can be improved in NoCs without sacrificing power-performance, by considering
the criticality of packet transmission. By playing a central role to facilitate
long term sustainability in NoCs, this research can substantially improve the
cost efficiency in building large data centers supporting our modern compute
intensive society. Major research insights will be disseminated through teaching
to develop relevant skill sets, lead to more sustainable future computer
systems, and benefit the community at large.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
The project explored a unique framework for designing aging resilient microarchitectures and routing algorithms for Network-on-Chips (NoCs).
Outcomes:
Year 1:
Intellectual Merit:
1) Algorithms for tackling aging in Exascale NoC systems published at CODES-ISSS 2014 and TVLSI 2014.
2) Algorithms for understanding the threat of compromised NoCs published at DAC 2014.
3) Algorithms for the Long Term Sustainability of Differentially Reliable Systems published at ICCD 2013.
Broader Impacts:
1) The PI gave a seminar at the AMD Research and Intel/Hudson, and sought indistrial avenues for the major findings from this project.
2) The PIs and their students gave presentation in conferences (e.g., 2014 DATE, 2014 DAC), and interacted with the audience in those venues.
3) Our work on exascale NoCs also received a nomination for the Best Paper Award at the CODES-ISSS 2014 conference.
4) The PIs' students gave seminars in the Graduate Colloquium to present these new research directions to a wider audience.
Year 2:
Intellectual Merit:
1) Algorithms for Understanding Timing Errors in the NoC published at ISLPED 2015.
2) Uncovering the tension between aging awareness and quality of service (QoS) in Exascale NoCs published at CODES-ISSS 2014.
3) Novel techniques for detection of a stealthy bandwidth denial attack on a NoC published at NOCS 2015.
Broader Impacts:
1) The PIs and their students also gave presentation in recent conferences (e.g., 2014 CODES-ISSS, 2015 DAC, 2015 ISLPED), and interacted with the audience in those venues.
2) The PIs organized a weekly reading group to critically analyze recent research from various top conferences and journals.
Year 3:
Intellectual Merit:
1) Combating Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms published at DATE 2016.
2) Tackling Voltage Emergencies in NoC through Timing Error Resilience.
Broader Impacts:
1) The PI and Co-I gave seminars at TUM Muchich and sought collaborative opportunities spawning from the major findings from this project.
2) The PIs and their students also gave presentation in recent conferences (e.g., 2016 DAC, NOCS 2015), and interacted with the audience in those venues.
Year 4:
Intellectual Merit:
1) Power Efficient Network-on-Chip Architecture for Near Threshold Computing published at ICCAD 2016.
2) Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms published at TVLSI 2017.
Broader Impacts:
1) Students from our group presented their work at DATE 2017 and ICCAD 2016 for dissemination to a wider community.
2) The Co-I attended DATE 2016 to interect with other members of the academia.
3) New projects were designed in the existing courses where students were encouraged to pursue new directions (e.g., NoC reliability related research projects in graduate courses).
4) The Co-I mentored undergraduate women at USU through the women's leadership initiative (WLI) program.
Year 5:
Intellectual Merit:
1) Security Measures Against a Rogue Network-on-Chip published at Journal of Hardware and Systems Security 2017.
2) Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC published at ISLPED 2018.
Broader Impacts:
1) Students from our group presented their work at DATE 2018 and ISLPED 2018 for dissemination to a wider community.
2) The PI and Co-I attended ISLPED 2018 to interact with other members of the academia.
3) The Co-I mentored undergraduate women at USU through the women's leadership initiative (WLI) program.
Last Modified: 11/15/2018
Modified by: Sanghamitra Roy
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