
NSF Org: |
CCF Division of Computing and Communication Foundations |
Recipient: |
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Initial Amendment Date: | January 31, 2013 |
Latest Amendment Date: | June 16, 2015 |
Award Number: | 1255193 |
Award Instrument: | Continuing Grant |
Program Manager: |
Sankar Basu
sabasu@nsf.gov (703)292-7843 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
Start Date: | April 1, 2013 |
End Date: | March 31, 2017 (Estimated) |
Total Intended Award Amount: | $180,000.00 |
Total Awarded Amount to Date: | $180,000.00 |
Funds Obligated to Date: |
FY 2014 = $30,000.00 FY 2015 = $30,000.00 |
History of Investigator: |
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Recipient Sponsored Research Office: |
400 HARVEY MITCHELL PKY S STE 300 COLLEGE STATION TX US 77845-4375 (979)862-6777 |
Sponsor Congressional District: |
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Primary Place of Performance: |
College Station TX US 77843-1260 |
Primary Place of
Performance Congressional District: |
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Unique Entity Identifier (UEI): |
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Parent UEI: |
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NSF Program(s): | Failure Resistant Systems(FRS) |
Primary Program Source: |
01001415DB NSF RESEARCH & RELATED ACTIVIT 01001516DB NSF RESEARCH & RELATED ACTIVIT |
Program Reference Code(s): | |
Program Element Code(s): |
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Award Agency Code: | 4900 |
Fund Agency Code: | 4900 |
Assistance Listing Number(s): | 47.070 |
ABSTRACT
Variability is a grand challenge that hinders the progress of semiconductor technology. Adaptive design is considered a promising approach for addressing this challenge, especially under increasingly tight chip power constraints. However, its application in practice is limited, largely due to the lack of systematic techniques for managing its overhead, complexity, and integration with existing design flows. This research will develop a design automation framework that optimizes the use of adaptivity resources, maximizes their efficiency, and balances the tradeoff with conventional design objectives. The key of this research is capturing the uncertainty and dynamics of adaptive designs in a lightweight manner, yet with high fidelity. New variability and adaptivity models will be investigated in conjunction with robust optimization methods. In addition, a formal technique will be studied to handle the tradeoffs among competing design objectives. Parallel computing techniques will also be explored to cope with the enormous problem sizes of current and emerging applications.
This research will strengthen some weak links in adaptive circuit technology and help pave a path toward its wide applications. It will simultaneously address variability and power challenges faced by nanometer semiconductor technologies. The potential improvement of chip power-efficiency will facilitate green computing technology. Furthermore, the proposed techniques will be applicable to next-generation device technologies and will therefore benefit the future of the semiconductor industry. This research will also serve as a test-bed for training students to understand synergies among various aspects of modern chip design processes.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
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PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
An adaptive circuit can autonomously change its configurations in response to process and/or aging variations and is considerably more power-efficient than the existing approach of over-design in combating variations. However, it can easily result in large area overhead that prevents it from wide applications. The overarching goal of this project is to build a framework that facilitates automatic design of adaptive circuits with systematic resource allocation such that the area overhead is restricted. The outcomes of this project are summarized as follows.
Timing Verification for Adaptive Integrated Circuits
In this project, new timing verification techniques are developed to handle adaptive circuits. Specifically, several adaptivity scenario pruning techniques are identified. A timing verification algorithm using these techniques along with statistical timing analysis is developed. Experimental results on benchmark circuits, including cases with 150K gates, demonstrate that the new techniques can achieve orders of magnitude speedup with less than 2% error compared to Monte Carlo simulations.
Joint Cell Placement and Adaptivity Clustering
To limit the overhead of adaptivity, cells are clustered into blocks and cells within a block share the same sensors and tuning. Given a cell placement, a new method is proposed to cluster cells considering both physical proximity and timing similarity among cells. After clustering, an incremental placement is performed to ensure that cells of the same block form a contiguous region. The incremental placement is an iterative min-cost flow approach such that the total cell movement is minimized. Experimental results on benchmark circuits, including cases of near one million gates, show that the proposed method spends less than 1% wirelength overhead in exchange for 1/3 to 2/3 area overhead reduction compared to a naive approach while retaining the same timing performance and power consumption.
Delay Sensor Deployment
Delay sensors tell if circuit delay variations are large enough and pose significant risk of timing violations. Meanwhile, delay sensors cause significant area overhead. In this regard, new techniques are developed to restrict delay sensor overhead and provide sufficient coverage for monitoring timing critical paths. The techniques include a greedy heuristic and a set cover based approach. Simulation result on a benchmark circuit of about 200K gates shows that the proposed techniques can improve the coverage by 3 to 5 times while using the same number of sensors compared to a previous work.
Control Design for Adaptive Circuits
Given sensor data, a circuit configuration is decided by a control circuit. Two general techniques for synthesizing adaptive circuit controller are developed. One is based on rules that are derived from network flow model and the other is a graph based finite state machine (FSM) design. Experiments are performed on benchmark circuits of 130K-959K gates using voltage interpolation as adaptive tuning knob. Compared to the conventional over-design, the FSM-based control allows about 45% leakage power reduction with about the same timing yield in presence of process and aging variations. The FSM-based control enables fine-grained adaptivity, which shows about 20% leakage power reduction compared to coarse-grained adaptivity.
Adaptivity Assignment in Conjunction with Conventional Circuit Optimization
Given a set of clustered adaptivity blocks, the adaptivity assignment is a sensitivity based heuristic. The circuit optimization is based on Lagrangian relaxation considering the adaptivity effects. Experimental results on benchmark circuits, including cases of 150K gates, show that the proposed algorithm can reduce adaptivity area overhead by more than 85% compared to a naive approach while retain the same timing performance and robustness.
Parallel Computing Technique Facilitating Fast Adaptive Circuit Design
Timing analysis costs considerable runtime, which is largely reduced through a new parallel computing technique based on GPU. Task scheduling and memory management techniques are developed so as to achieve about 100X speedup on benchmark circuits. A CPU-GPU pipelining technique is proposed and can reduce the runtime of adaptivity assignment by over 40%. The adaptivity assignment is jointly performed with gate implementation selection, whose runtime is reduced by 5X through multi-threading on 8-core CPU processor.
Overall Design Flow Validation for Adaptive Circuits
The overall adaptive design flow incorporating the proposed techniques is validated on a circuit of about 200K gates. The initial placement is generated by Cadence Encounter using Nangate Open Cell Library. Then, our clustering and incremental placement are performed. Next, adaptivity optimization is performed such that only a subset of clusters are assigned with adaptivity. For those adaptive blocks (clusters), control circuits and delay sensors are added. Then, routing is conducted using Cadence Encounter. The adaptivity is based on voltage interpolation. The simulation results show that our method can reduce leakage power by 39% compared to the conventional over-design while achieving the same timing yield.
Broader Impact
The techniques developed in this project can be easily extended to other design fields. The knowledge obtained from this project is disseminated through technical publications and partly included in the curriculums at Texas A&M University.
Last Modified: 06/28/2017
Modified by: Jiang Hu
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