ABSTRACT

Emerging memory technologies such as Magnetoresistive random-access memory (MRAM), Phase-change memory (PCRAM), and Resistive random-access memory (RRAM) are being explored as potential alternatives for future computing systems. However, traditional memory design methodologies are not sufficient to address probabilistic behaviors, which are caused by process variations and the intrinsic randomness in the physical mechanisms (e.g., thermal fluctuations) of these emerging technologies.

The objective of this research is to develop a design methodology called STatistical Emerging Memory Simulator (STEMS) for circuit/architecture designs with such emerging memory technologies. The intellectual merits include the following: (1) developing a generic statistical characterization formalism to link the emerging memory cell design specifications with design variables, process variations and environmental fluctuations, (2) deriving a variation-aware compact memory cell model to fulfill the demands of the statistical design optimizations at cell and array levels, and (3) investigating a statistical memory design methodology to explore the tradeoffs among memory structure, implementation cost, and design specifications for various system requirements. The proposed research will fundamentally change the design methodologies for future memory technologies, initiate an innovative direction in memory designs, and optimize and balance the new design characteristics of emerging memories under architectural considerations, inspiring the transition of design philosophy from the deterministic era to the probabilistic era. The proposed techniques provide a complementary perspective to the existing probabilistic system and architectural research while emphasizing the yield and probabilistic properties of memory designs.

This project will facilitate further advances and wider adoption of the emerging memory technologies by the semiconductor industry. Innovations in design methods and memory modeling will have an impact on the way in which semiconductor memory chips are designed and fabricated. Undergraduate and graduate students involved in this research will be trained for the next-generation semiconductor industry workforce.

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