Award Abstract # 1149773
CAREER: Holistic System Solutions for Empowering Parallel Programmers

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: REGENTS OF THE UNIVERSITY OF MICHIGAN
Initial Amendment Date: March 26, 2012
Latest Amendment Date: September 3, 2015
Award Number: 1149773
Award Instrument: Continuing Grant
Program Manager: Anindya Banerjee
abanerje@nsf.gov
 (703)292-7885
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: April 1, 2012
End Date: March 31, 2018 (Estimated)
Total Intended Award Amount: $538,671.00
Total Awarded Amount to Date: $538,671.00
Funds Obligated to Date: FY 2012 = $312,279.00
FY 2015 = $226,392.00
History of Investigator:
  • Satish Narayanasamy (Principal Investigator)
    nsatish@eecs.umich.edu
Recipient Sponsored Research Office: Regents of the University of Michigan - Ann Arbor
1109 GEDDES AVE STE 3300
ANN ARBOR
MI  US  48109-1015
(734)763-6438
Sponsor Congressional District: 06
Primary Place of Performance: University of Michigan Ann Arbor
3003 South State St. Room 1062
Ann Arbor
MI  US  48109-1271
Primary Place of Performance
Congressional District:
06
Unique Entity Identifier (UEI): GNJ7BBP73WE9
Parent UEI:
NSF Program(s): Software & Hardware Foundation
Primary Program Source: 01001213DB NSF RESEARCH & RELATED ACTIVIT
01001516DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 1045, 7329, 7943
Program Element Code(s): 779800
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

The central vision of this project is to bring parallel programming, which continues to be a daunting task to this day even for experts, to mainstream programmers. The fundamental challenge is that the concurrency semantics defined by memory models of popular parallel languages are too weak. This project is investigating solutions that span from processors to languages to enable stronger memory consistency models starting with sequential consistency, but goes far further in achieving much stronger concurrency semantics such as determinism at the language-level. The end goal is to find solutions that provide the best of both worlds: sequential semantics and parallel performance. A set of correctness and performance enhancing tools that exploit the stronger concurrency semantics are also being developed.

Advances in computing have relied on the exponential growth in processor performance. Unfortunately, unlike in the past, successive generations of processors can no longer improve sequential performance because of technology constraints. The burden has shifted to software developers who must now evolve to take advantage of parallelism in multi-core processors. Unfortunately, parallel programming continues to be a daunting task to this day even for experts. This project is developing solutions that can bring parallel programming to mainstream programmers by dramatically simplifying the process of developing, debugging, and maintaining parallel software. Programmer productivity tools developed as part of this research will be directly beneficial to students, software developers and researchers. By involving colleagues in industry, this project could serve as a catalyst to bring the software and processor industry together to solve a problem that is common to both: enabling mainstream programmers to take advantage of multi-core architectures.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

Note:  When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

Abhayendra Singh and Satish Narayanasamy and Daniel Marino and Todd D. Millstein and Madanlal Musuvathi "A Safety-First Approach to Memory Models" IEEE Micro , v.33 , 2013 , p.96-104
Abhayendra Singh, Shaizeen Aga, and Satish Narayanasamy "Efficiently enforcing strong memory ordering in GPUs" International Conference on Microarchitecture (MICRO). , 2015
Chun-Hung Hsiao, Satish Narayanasamy, Essam Muhammad Idris Khan, Cristiano L. Pereira, Gilles A. Pokam: "AsyncClock: Scalable Inference of Asynchronous Event Causality." Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017. , 2017
Daniel Marino and Abhayendra Singh and Todd D. Millstein and Madanlal Musuvathi and Satish Narayanasamy "DRF\emph{x}: An Understandable, High Performance, and Flexible Memory Model for Concurrent Languages" {ACM} Trans. Program. Lang. Syst. , v.38 , 2016 , p.16:1--16:
Daniel Marino, Todd Millstein, Madanlal Musuvathi, Satish Narayanasamy, Abhayendra Singh "The Silently Shifting Semicolon" Inaugural Summit on Advances in Programming Languages (SNAPL). , 2015
David Devecsery, Peter M. Chen, Jason Flinn, Satish Narayanasamy: "Optimistic Hybrid Analysis: Accelerating Dynamic Analysis through Predicated Static Analysis." Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018. , 2018
Shaizeen Aga, Sriram Krishnamoorthy, and Satish Narayanasamy "CilkSpec: optimistic concurrency for Cilk" roceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC). , 2015
Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, Reetuparna Das "Compute Caches" 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017. , 2017

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

This project made significant advancements that can help bring parallel programming to the masses. It developed efficient solutions for enabling strong concurrency semantics and several programmer productivity tools for reasoning about concurrent executions.

At the heart of concurrency semantics is the memory model. A memory model defines the set of possible orders in which memory operations from different threads can interleave and the possible values a read can return. Even this fundamental property is not cleanly defined in the memory models of popular languages such as C++ and Java, and remains a topic for active debate. Sequential consistency (SC) is widely recognized as a strong concurrency semantics that is intuitive for programmers. This project provided strong evidence that SC can be guaranteed at the language-level for only a small performance overhead (~2%). An LLVM-based SC-preserving open-source compiler was released to the public. The project also showed that simple extensions to commodity processors, including accelerators such as GPUs, can significantly lower the overhead of fences and enable SC in practice.

This project also developed novel program analysis methods and tools for analyzing and debugging executions of concurrent programs. Ability to deterministically replay a concurrent execution can significantly help a programmer understand and debug. However, recording non-determinism due to data-races incurred significant performance overhead. This project used profile-based static analysis named Chimera to produce a practically feasible low-overhead recording solution. This project also extended the capabilities of a dynamic data-race detector to efficiently reason about asynchronous concurrency in mobile and web applications. 

 


Last Modified: 08/16/2018
Modified by: Satish Narayanasamy

Please report errors in award information by writing to: awardsearch@nsf.gov.

Print this page

Back to Top of page