For many decades we have taken for granted the fact that computer performance has been doubling every one or two years. This extraordinary growth created an industry that has impacted almost every aspect of our lives – from the way we work to the way we play, communicate or provide healthcare. This revolution was enabled in no small part by one of the computer’s core technologies: the microprocessor. Over the last fifty years microprocessors have benefited tremendously from technology innovations that have delivered more and faster transistors with every new generation. Unfortunately, that technology has reached an impasse in recent years, as transistors have approached low-nanometer dimensions. Transistors are so small in the latest technology that about 6 million of them would fit in the period at the end of this sentence. These transistors are less predictable, less reliable and their energy efficiency is increasing very slowly. Building chips with these minute transistors is likely the most significant manufacturing challenge humans have ever undertaken.

The work conducted as part of this project has addressed the challenge of designing faster and more energy efficient microprocessors under the most adverse technological challenges our industry has ever faced. The principal approach used in this undertaking is a new computing paradigm generally referred to as “Near-Threshold Computing” (NTC).  The technique relies on lowering the supply voltage (Vdd) of a chip to a level only slightly higher than the threshold voltage (Vth) – the level at which transistors begin conducting current. Vdd is the most powerful knob for improving energy efficiency, because it impacts both dynamic and static power super-linearly. Even though NTC significantly reduces chip speed, it allows for many more computation units (cores) to be powered on simultaneously for the same power cost. Multi-threaded workloads that can take advantage of the increased parallelism can run much more efficiently at NTC. Experimental data shows these applications can attain 8x to 10x higher energy efficiency at NTC compared to conventional super-threshold computing (STC).

Unfortunately, Near-Threshold Computing faces multiple challenges before it can become a mainstream technology. This is because NTC is less reliable than conventional technology, requiring additional protection against failures. NTC also amplifies the effects of process (post-manufacturing) and runtime variability.

This project has addressed many of the limitations of NTC to bring the technology closer to reality. One such solution allows each core on a chip to periodically switch between two different maximum frequencies, on a predetermined schedule. The schedule is different for each core and is chosen such that core frequencies average to the same value over a finite interval. This means that cores that are inherently slow are scheduled to spend more time on the high voltage rail while those that are fast will spend more time on the low voltage rail. The result is a CMP that achieves performance homogeneity from an underlying heterogeneous fabric. 

Another significant challenge of NTV operation is the increased sensitivity to voltage fluctuations. These fluctuations are caused by abrupt changes in power demand triggered by processor activity variation with workload. If the voltage deviates too much from its nominal value, it can lead to so-called “voltage emergencies,” which can cause timing and memory retention errors. As the number of cores in future chips increases, chip-wide coordinated activity such as that forced by global synchronization in multithreaded applications leads to large power fluctuations, which in turn can cause emergencies. This project developed hardware/software co-design solutions that enlist software support to addr...

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