| NSF Org: |
CCF Division of Computing and Communication Foundations |
| Recipient: |
|
| Initial Amendment Date: | May 31, 2011 |
| Latest Amendment Date: | May 31, 2011 |
| Award Number: | 1115556 |
| Award Instrument: | Standard Grant |
| Program Manager: |
Sankar Basu
sabasu@nsf.gov (703)292-7843 CCF Division of Computing and Communication Foundations CSE Directorate for Computer and Information Science and Engineering |
| Start Date: | July 1, 2011 |
| End Date: | June 30, 2015 (Estimated) |
| Total Intended Award Amount: | $175,000.00 |
| Total Awarded Amount to Date: | $175,000.00 |
| Funds Obligated to Date: |
|
| History of Investigator: |
|
| Recipient Sponsored Research Office: |
800 WEST CAMPBELL RD. RICHARDSON TX US 75080-3021 (972)883-2313 |
| Sponsor Congressional District: |
|
| Primary Place of Performance: |
800 WEST CAMPBELL RD. RICHARDSON TX US 75080-3021 |
| Primary Place of
Performance Congressional District: |
|
| Unique Entity Identifier (UEI): |
|
| Parent UEI: |
|
| NSF Program(s): | Software & Hardware Foundation |
| Primary Program Source: |
|
| Program Reference Code(s): |
|
| Program Element Code(s): |
|
| Award Agency Code: | 4900 |
| Fund Agency Code: | 4900 |
| Assistance Listing Number(s): | 47.070 |
ABSTRACT
The advance of VLSI technology has reached to 32nm feature size and below. For such a nano-scale process, lithography no longer produces the ideal shape/dimension of circuit components in a silicon wafer, and the corresponding electrical parameters may vary as large as 1/3 or more. A major concern in VLSI design is how to evaluate the circuits/systems performance made in such nano-scale process. In the other words, we want to know how much the performance specs will change due to variation in circuit parameters from their nominal values caused by the process uncertainties. The current research on performance robustness analysis is developed mainly along the line of the Monte-Carlo sampling method, or stochastic and statistical analysis methods. They all require a high level of computation complexity to achieve the required accuracy and one would like to avoid the evaluation of large number of samples to validate the performance range of a VLSI circuit/system.
In this research the PIs propose a novel method for VLSI circuit performance robustness analysis which does not require evaluation of large numbers of samples. Instead, it computes only a few critical polynomials in frequency domain, or critical systems in time domain. It is a fundamentally new way to analyze VLSI circuit performance robustness. The consequent leap of computation efficiency would make nano-scale VLSI circuit design and its performance robustness analysis practically possible. The objectives of this project are: (i) to develop a solid theoretical basis for the performance robustness analysis of VLSI circuits in both frequency and time domains; (ii) to develop an efficient, novel method for computing VLSI circuit performance variation bounds and distribution (due to the process variation) without using the Monte-Carlo method.
The broad impact of this project will be its potentially transformative effect on the robust analysis methods for VLSI circuits. This research will be integrated into the graduate education of the Ph.D. students at the two universities involved, and disseminated by publications in journals and presentations at conferences, a workshop and collaboration with industry, and will hopefully contribute to broad thinking across multiple disciplines.
PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH
Note:
When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external
site maintained by the publisher. Some full text articles may not yet be available without a
charge during the embargo (administrative interval).
Some links on this page may take you to non-federal websites. Their policies may differ from
this site.
PROJECT OUTCOMES REPORT
Disclaimer
This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.
The collaborative research teams of UT Dallas (UTD) and UNC Charlotte (UNCC) supported by this NSF collaborative project grant have 29 papers for publication with the acknowledgement of NSF Grants (1115556-UTD and/or 1115564-UNCC), among that 25 papers as published (7 journal papers: 3-UNCC, 4-UTD; and 18 conference papers: 9-UNCC, 4-UTD, 5-joint) and 4 papers as accepted recently (3 journal papers: 1-UNCC, 2-UTD; and 1 conference paper-UTD).
The collaborative research teams have proposed and developed new methods to significantly reduce the sampling test numbers and time for the robust performance analysis and design of VLSI circuits with severe parameter value variations due to nano-scale process, but also provided the theoretical derivation and analysis for their new methods as in the publications.
To enhance the broad impacts, the teams have also made presentations of these 18 conference papers at various professional conferences. Furthermore, the PI at UNCC was invited to present his research results at Japan Tohoku University in 2012, and at the 4th Annual Asia-Pacific Summer School (APSS) in Smart Structures Technology for 50 international graduate students from US, China, Japan and S. Korea in August 2011, who were supported by NSF, NSFC, JSPS, JST, KOSEF and SISTeC, respectively. The PI at UTD was invited to present a special talk at the 10th IEEE International Conference on ASIC (Application Specific Integrated Circuit) in 2013. The project also supported to train graduate students at two universities, including two women, and they have graduated and are working in industry in US.
Last Modified: 09/14/2015
Modified by: Dian Zhou
Please report errors in award information by writing to: awardsearch@nsf.gov.
