Award Abstract # 1054339
CAREER: Design of Reconfigurable Power and Area-Efficient Nanophotonic Architectures for Future Multi-cores

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: OHIO UNIVERSITY
Initial Amendment Date: December 3, 2010
Latest Amendment Date: April 29, 2015
Award Number: 1054339
Award Instrument: Continuing Grant
Program Manager: Sankar Basu
sabasu@nsf.gov
 (703)292-7843
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: April 1, 2011
End Date: March 31, 2018 (Estimated)
Total Intended Award Amount: $407,578.00
Total Awarded Amount to Date: $523,840.00
Funds Obligated to Date: FY 2011 = $160,676.00
FY 2012 = $92,254.00

FY 2013 = $91,504.00

FY 2014 = $96,616.00

FY 2015 = $82,790.00
History of Investigator:
  • Avinash Karanth (Principal Investigator)
    karanth@ohio.edu
Recipient Sponsored Research Office: Ohio University
1 OHIO UNIVERSITY
ATHENS
OH  US  45701-2979
(740)593-2857
Sponsor Congressional District: 12
Primary Place of Performance: Ohio University
1 OHIO UNIVERSITY
ATHENS
OH  US  45701-2979
Primary Place of Performance
Congressional District:
12
Unique Entity Identifier (UEI): LXHMMWRKN5N8
Parent UEI:
NSF Program(s): Software & Hardware Foundation,
DES AUTO FOR MICRO & NANO SYST
Primary Program Source: 01001112DB NSF RESEARCH & RELATED ACTIVIT
01001213DB NSF RESEARCH & RELATED ACTIVIT

01001314DB NSF RESEARCH & RELATED ACTIVIT

01001415DB NSF RESEARCH & RELATED ACTIVIT

01001516DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 1045, 7941, 7945, 9218, 9251, HPCC
Program Element Code(s): 779800, 794500
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

As the number of cores increases on the same die, computer architects and system designers have focused their attention to the on-chip network that is used for communication between the cores. Two of the major problems facing on-chip architectures are excessive power dissipation and reduced network performance. One approach to extend the performance of future multi-cores is to integrate new technologies, such as nano-photonics into the electronic design flow. Nano-photonics offers a scalable, low power per bit and a high- performance technology solution to current electrical signaling and interconnect bottlenecks. This research seeks to exploit this emerging field of nano-photonics and design reconfigurable, energy-efficient and high- performance on-chip architectures and switching interconnects. The goal of this research is to develop interconnects that can dynamically tune to the application and regulate power and bandwidth without system intervention.

The proposed research will have a significant impact on the design of future multi-cores using nano-photonics. The proposed research will make advances in the understanding of the interplay between performance, energy, hardware complexity and reconfigurability. This research will also play a major role in education by integrating research with teaching and training. The educational goal of this multi-disciplinary and multi-faceted proposed research is to expose undergraduate and graduate students to diverse technological advancements with an emphasis on critical analysis and reasoning to overcome limitations of current technologies. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

Note:  When clicking on a Digital Object Identifier (DOI) number, you will be taken to an external site maintained by the publisher. Some full text articles may not yet be available without a charge during the embargo (administrative interval).

Some links on this page may take you to non-federal websites. Their policies may differ from this site.

(Showing: 1 - 10 of 15)
Boraten, Travis and Kodi, Avinash "Mitigation of Hardware Trojan Based Denial-of-Service Attack for Secure NoCs" Journal of Parallel Distributed Computing , v.111 , 2018 , p.24 10.1016/j.jpdc.2017.06.014
Brian Neel, Randy Morris, Dominic DiTomaso and Avinash Kodi "SPRINT: Scalable Photonic Switching Fabric for High-Performance Computing (HPC)" Journal of Optical Communications and Networking (JOCN), Special Issue on Enabling Devices for Scalable Networks , v.9 , 2012
David W. Matolak, Avinash Kodi, Savas Kaya, Dominic DiTomaso, Soumyasanta Laha and William Rayess "Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices" IEEE Wireless Communications Magazine, Special Issue on Wireless Communication at Nanoscale , v.19 , 2012 , p.58
David W. Matolak, Savas Kaya, and Avinash Kodi "Channel Modeling for Wireless Networks-on-Chips" IEEE Wireless Communications Magazine , v.51 , 2013 , p.180
D. DiTomaso and A. K. Kodi and A. Louri and R. Bunescu "Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures" IEEE Transactions on Computers , v.64 , 2015 , p.3555-3568 10.1109/TC.2015.2401013
D. DiTomaso and A. Kodi and D. Matolak and S. Kaya and S. Laha and W. Rayess "A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors" IEEE Transactions on Parallel and Distributed Systems , v.26 , 2015 , p.3289-3302 10.1109/TPDS.2014.2383384
Dominic DiTomaso and Avinash Kodi and Ahmed Louri and Razvan Bunescu "Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures" IEEE Transactions on Computers , 2015 10.1109/TC.2015.2401013
Dominic DiTomaso and Avinash Kodi and David W. Matolak and Savas Kaya and Soumyasanta Laha and William Rayess "A-WiNoC: Adaptive Wireless Network-on-Chips (NoCs) Architecture for Future Multicores" IEEE Transactions on Parallel and Distributed Systems , 2014 10.1109/TPDS.2014.2383384
Dominic DiTomaso, Randy Morris, Avinash Kodi, Ashwini Sarathy and Ahmed Louri "Extending the Energy-Efficiency and Performance with Channel Buffers, Crossbars and Topology Analysis for NoCs" IEEE Transactions on VLSI , v.21 , 2013 , p.2141
J. Wu and A. K. Kodi and S. Kaya and A. Louri and H. Xin "Monopoles Loaded With 3-D-Printed Dielectrics for Future Wireless Intrachip Communications" IEEE Transactions on Antennas and Propagation , v.65 , 2017 , p.6838 10.1109/TAP.2017.2758400
Matthew Kennedy and Avinash Karanth Kodi "CLAP-NET: Bandwidth adaptive optical crossbar architecture" Journal of Parallel and Distributed Computing , v.100 , 2017 , p.130 - 139 http://dx.doi.org/10.1016/j.jpdc.2016.05.004
(Showing: 1 - 10 of 15)

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

As on-chip power consumption becomes the most critical barrier, we need disruptive technology solution such as silicon photonics that can scale in capacity and reduce power footprint while delivering scalable bandwidth. Photonic interconnects can provide high interconnect bandwidth by combining multiple wavelengths, provide minimal access latencies, and high power-efficiency that remains independent of capacity and distance for on-chip communications. In this project, we have explored several aspects of utilizing photonics for NoCs. In R-3PO, we designed a 3D stacked photonic architecture where multiple layers enabled higher bandwidth density, simplified layout design, and reduced network power [1]. Unlike a global crossbar, we developed a decomposed crossbar architecture on multiple photonic layers with optical vias to prevent waveguide crossings and reduce power consumption. As multicores run diverse scientific and commercial applications, networks that can adapt to communication traffic will yield substantial performance gains while optimizing the resources such as wavelengths and waveguides. In R-3PO, we implement a reconfiguration algorithm that uses hardware counters to track link and buffer utilization to decide which links to reconfigure and adapt network bandwidths based on application demands. In PROBE, we tackle the static power consumption of external laser by predicting channel utilization and scaling the number of wavelengths and waveguides [2]. In PULSE, we extend the performance and reduce power consumed in shared-memory multicores that use snoopy-based cache coherence protocols by multicasting transactions to select cores that cache the block instead of broadcasting to all nodes [3]. In CLAPNET, we propose clockwise and counter-clockwise communication to reduce the laser power loss due to requests and responses traveling different path lengths [4]. The CLAP-NET design leverages shared waveguides to enable dynamic bandwidth allocation for improved network throughput, and a decomposed crossbar with reduced optical insertion losses and power consumption. In Laser Pooling, we propose sharing available laser power between all links of the network, such that laser power may be released from idle links and claimed by another link both statically and dynamically [5]. We refer to this as pooling laser power between the links of the network to maximize energy savings with marginal performance impact. To reduce the static power, in PEARL, we propose a dynamic laser scaling technique that predicts the power level for the next epoch using the buffer occupancy of previous epoch using machine learning techniques [6]. In terms of broader impact, this project has provided training to graduate and undergraduate students in modeling and simulation of NoC architectures and has resulted in 5 MS theses and 2 PhD dissertations. Further, the results of the project have been widely disseminated with journals and conference/workshop presentations.

 

References:

  1. Randy Morris, Avinash Kodi, Ahmed Louri and Ralph Whaley, “3D Stacked Nanophotonic Architecture with Minimal Reconfiguration,” IEEE Transactions on Computers (TC), vol. 63, no. 1, pp. 243-255, January 2014.
  2. Li Zhou and Avinash Kodi, “PROBE: Prediction-based Optical Bandwidth Scaling in Energy-Efficient NoCs,” ACM/IEEE 7th International Symposium on Network-on-Chips (NoCs), Tempe, Arizona, April 21-24, 2013.
  3. Randy Morris, Evan Jolley and Avinash Kodi, “Extending the Performance and Energy-Efficiency of Nanophotonic Interconnects for Shared Memory Multicores,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 25, no. 1, pp. 83-93, January 2014.
  4. Matthew Kennedy and Avinash Kodi, “CLAP-NET: Bandwidth Adaptive and Power Regulated Optical Crossbar Architecture,” Elsevier Journal of Parallel and Distributed Systems (JPDC), vol. 100, pp. 130-139, February 2017.
  5. Matthew Kennedy and Avinash Kodi, “Laser Pooling: Static and Dynamic Laser Power Allocation for On-Chip Optical Interconnects,” IEEE/OSA Journal of Lightwave Technology (JLT), vol. 35, no. 15, pp. 3159-3167, August 2017.
  6. Scott VanWinkle, Avinash Kodi, Razvan Bunescu and Ahmed Louri, “Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning,” 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA-24), Vienna, Austria, February 24-28, 2018.

 


Last Modified: 05/19/2018
Modified by: Avinash K Kodi

Please report errors in award information by writing to: awardsearch@nsf.gov.

Print this page

Back to Top of page