Award Abstract # 0963737
Rethinking Parallel Execution, Architecture, and Software

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF WISCONSIN SYSTEM
Initial Amendment Date: May 6, 2010
Latest Amendment Date: April 10, 2012
Award Number: 0963737
Award Instrument: Continuing Grant
Program Manager: Almadena Chtchelkanova
achtchel@nsf.gov
 (703)292-7498
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: June 1, 2010
End Date: May 31, 2014 (Estimated)
Total Intended Award Amount: $799,589.00
Total Awarded Amount to Date: $799,589.00
Funds Obligated to Date: FY 2010 = $532,143.00
FY 2012 = $267,446.00
History of Investigator:
  • Gurindar Sohi (Principal Investigator)
    sohi@cs.wisc.edu
Recipient Sponsored Research Office: University of Wisconsin-Madison
21 N PARK ST STE 6301
MADISON
WI  US  53715-1218
(608)262-3822
Sponsor Congressional District: 02
Primary Place of Performance: University of Wisconsin-Madison
21 N PARK ST STE 6301
MADISON
WI  US  53715-1218
Primary Place of Performance
Congressional District:
02
Unique Entity Identifier (UEI): LCLSJAGTNZQ7
Parent UEI:
NSF Program(s): COMPILERS,
COMPUTER ARCHITECTURE,
PROGRAMMING LANGUAGES
Primary Program Source: 01001011DB NSF RESEARCH & RELATED ACTIVIT
01001213DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 9218, HPCC
Program Element Code(s): 732900, 794100, 794300
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

Computing today is at a critical juncture as processors move away from uniprocessors to multicore processors. Without innovations in how to writeprograms to make use of multiple processing cores, software vendors will no longer have access to increasing processing performance, a phenomenon that has driven the growth of the computer industry for over four decades. Realizing the enormity of the situation many leaders have put parallel computing high on their list of critical research issues and many researchers are trying to build on four decades of knowledge to make progress in this critical area.

This research is investigating a novel approach to attacking this critical problem, one that is counter to much of the prevailing wisdom on parallel execution. The approach couples widely used sequential programrepresentations with a novel dynamic parallel execution model to achieve parallel execution. Initial experience with this new approach has been very promising: it can achieve parallelism comparable to, and sometimes better than, applications parallelized with traditional techniques, but can do so without the drawbacks of the traditional techniques. This work investigates the applicability and effectiveness of this new approach for a variety of problem areas, including database, networking, and embedded applications. The work will also investigate the impact of the novel parallel execution model on the design of processors and chip multiprocessors. Broader impacts include a potential transformation in how a variety of important application programs are written for parallel execution on multicore processors and the consequent design of such processors.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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Gagan Gupta and Gurindar S. Sohi "Dataflow execution of sequential imperative programs on multicore architectures" 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011 , 2011 , p.59

PROJECT OUTCOMES REPORT

Disclaimer

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content.

Computing devices are pervasive, and most common devices have multiple processing cores (i.e., are multicore processors).  Making efficient use of multicore processors is a challenging problem whose solution is critical to the continued advances in, and proliferation of, computing devices.

The research project made two important contributions to addressing the challenges that future multicore processors are likely to face.  First, the research developed a novel programming approach where the program is an ordered program, which makes programming easier, yet the program is executed in parallel “under the hood”.  This proposed approach attempts to replicate the model that was very successful in facilitating advances in microprocessors from about 1995 onwards---where sequential programs were transparently executed in parallel to improve performance---but does so for multicore processors.  The new approach was tested out for a variety of application programs on a variety of commercial platforms, achieving results that were better than the traditional parallel programming approaches.  Second, the project developed a novel approach to achieve the efficient execution of a parallel program, without additional effort required from the programmer of the application.  Though the problem has been known for a while, a practical solution has been challenging because of the complex interplay between the program and underlying host system.   Moreover, the importance of achieving efficient execution is continuing to increase. The techniques developed in the project optimize a program’s parallel execution to best match the hardware resource capabilities, while optimizing diverse efficiency metrics.  Experimental results on different commercial platforms were carried out to demonstrate the effectiveness of the techniques over existing approaches.  In addition to the above, the project developed a variety of other techniques to improve the design of multicore processors.

The results of the project have the potential to have significant impact on the design of multicore processors across the computing spectrum ranging from smart phones to servers.  It is likely that the techniques developed in the research will either be directly employed, or will influence the techniques that are widely deployed in ubiquitous computing devices in the next decade.  In addition, the research project supported three graduate research assistants. They were trained to become independent researchers and engineers who are expected to not only use their training to develop new information technology products, but also to further train and mentor others in computer technology-related research and product development.

 


Last Modified: 07/03/2014
Modified by: Gurindar S Sohi

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