Award Abstract # 9628999
Presidential Faculty Fellows/Presidential Early Career Awards for Scientists and Engineers (PFF/PECASE): Power Estimation and Optimization in IC Design

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF SOUTHERN CALIFORNIA
Initial Amendment Date: July 10, 1997
Latest Amendment Date: June 26, 2000
Award Number: 9628999
Award Instrument: Continuing Grant
Program Manager: Robert B Grafton
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: July 15, 1997
End Date: September 30, 2000 (Estimated)
Total Intended Award Amount: $200,000.00
Total Awarded Amount to Date: $200,000.00
Funds Obligated to Date: FY 1997 = $100,000.00
FY 1998 = $100,000.00
History of Investigator:
  • Massoud Pedram (Principal Investigator)
    pedram@usc.edu
Recipient Sponsored Research Office: University of Southern California
3720 S FLOWER ST FL 3
LOS ANGELES
CA  US  90033
(213)740-7762
Sponsor Congressional District: 34
Primary Place of Performance: University of Southern California
3720 S FLOWER ST FL 3
LOS ANGELES
CA  US  90033
Primary Place of Performance
Congressional District:
34
Unique Entity Identifier (UEI): G88KLJR3KYT5
Parent UEI:
NSF Program(s): DES AUTO FOR MICRO & NANO SYS,
COMPUTER SYSTEMS ARCHITECTURE
Primary Program Source: app-0197 
app-0198 
Program Reference Code(s): 9215, 9296, HPCC
Program Element Code(s): 471000, 471500
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This is developing a methodology and efficient techniques for evaluating and/or predicting power dissipation of CMOS circuits. The major components of the proposed methodology are survey sampling techniques, automata-based sequence compaction techniques, a behavioral/logic level co-simulation engine, regression-based power macro-modeling techliques, and information-theoretic models of power dissipation. Special emphasis is being given to parasitic capacitance estimation, input data modeling, impact of memory hierarchy and circuit architecture, and effects of nonlinear delay equations and custom wire load models on accuracy/efficiency trade-offs of the estimators. Concurrently, CAD methodologies and techniques for minimizing the power dissipation in VLSI circuits and systems are being developed. These are: low power optimization techniques and prototype software programs for system-level partitioning and hardware/software codesign, communication synthesis, multiple supply voltage scheduling, activity-driven register allocation and binding, bus encoding, state assignment for interacting finite state machines, logic restructuring and simplification, timing-driven placement, routing and zero-skew clock tree construction. Finally, power management techniques such as (serial or parallel) gated clocks, stoppable clocks, and dynamic switching between power modes are being studied and automated.

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