Award Abstract # 9457392
NSF Young Investigator: Low Power VLSI Design

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF SOUTHERN CALIFORNIA
Initial Amendment Date: August 8, 1994
Latest Amendment Date: July 2, 1997
Award Number: 9457392
Award Instrument: Continuing Grant
Program Manager: Robert B Grafton
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: September 1, 1994
End Date: August 31, 1999 (Estimated)
Total Intended Award Amount: $312,500.00
Total Awarded Amount to Date: $250,000.00
Funds Obligated to Date: FY 1994 = $25,000.00
FY 1995 = $100,000.00

FY 1996 = $62,500.00

FY 1997 = $62,500.00
History of Investigator:
  • Massoud Pedram (Principal Investigator)
    pedram@usc.edu
Recipient Sponsored Research Office: University of Southern California
3720 S FLOWER ST FL 3
LOS ANGELES
CA  US  90033
(213)740-7762
Sponsor Congressional District: 34
Primary Place of Performance: University of Southern California
3720 S FLOWER ST FL 3
LOS ANGELES
CA  US  90033
Primary Place of Performance
Congressional District:
34
Unique Entity Identifier (UEI): G88KLJR3KYT5
Parent UEI:
NSF Program(s): DES AUTO FOR MICRO & NANO SYS,
COMPUTER SYSTEMS ARCHITECTURE
Primary Program Source: app-0194 
app-0195 

app-0196 

app-0197 
Program Reference Code(s): 9215, 9297, HPCC
Program Element Code(s): 471000, 471500
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This research investigates modeling and estimation of power consumption as well as techniques for minimizing power at the various levels of design abstraction (layout, logic, register- transfer and behavioral levels). Principles and methods to guide the design of power efficient electronic systems are being explored; and the impact of availability of low-power design techniques on chip, module, and system level designs is being assessed. Topics being investigated include: spatio-temporal power estimation; state assignment for low power; power dissipation in boolean networks; common subexpression extraction; and FPGA synthesis for low power.

Please report errors in award information by writing to: awardsearch@nsf.gov.

Print this page

Back to Top of page