Award Abstract # 9211668
RIA: Combined Logic Synthesis and Physical Design

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient: UNIVERSITY OF SOUTHERN CALIFORNIA
Initial Amendment Date: May 22, 1992
Latest Amendment Date: July 30, 1992
Award Number: 9211668
Award Instrument: Standard Grant
Program Manager: Robert B Grafton
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: June 1, 1992
End Date: May 31, 1995 (Estimated)
Total Intended Award Amount: $100,000.00
Total Awarded Amount to Date: $100,000.00
Funds Obligated to Date: FY 1992 = $100,000.00
History of Investigator:
  • Massoud Pedram (Principal Investigator)
    pedram@usc.edu
Recipient Sponsored Research Office: University of Southern California
3720 S FLOWER ST FL 3
LOS ANGELES
CA  US  90033
(213)740-7762
Sponsor Congressional District: 34
Primary Place of Performance: DATA NOT AVAILABLE
Primary Place of Performance
Congressional District:
Unique Entity Identifier (UEI): G88KLJR3KYT5
Parent UEI:
NSF Program(s): CISE Research Resources,
DES AUTO FOR MICRO & NANO SYS
Primary Program Source:  
Program Reference Code(s): 9215
Program Element Code(s): 289000, 471000
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

This research is on finding efficient techniques for producing solutions to logic synthesis and physical design problems both simultaneously and interactively. Two problem areas are being investigated: integrating logic synthesis with physical design; and layout algorithms for Boolean networks. In the first area, a prototype synthesis system which is capable of making synthesis decisions based on both logic level information and detailed data about the interconnecting wires and characteristics of the physical media is being developed. The key idea is to generate a placement of the Boolean network that captures the structure of the layout. The correspondence between logic and layout representations is maintained during iterations. Both technology independent and technology dependent logic transformations are accommodated. In the second area, ways to assign the I/O pads or place the nodes of an unmapped Boolean network, where the nodes still have technology independent logic realizations, are being investigated. Physical design tools which effectively capture the structural characteristics of Boolean networks and can handle nodes of inexact or approximate area, intrinsic delay and drive are being developed. Accurate and efficient modeling of interconnect during logic synthesis and layout plays a key role in the algorithm development.

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