Due to technology scaling, circuits are becoming more susceptible toparticle-strike induced soft errors that may cause system crash or silent datacorruption (SDC). Our take on this is that the resilience must be achieved in anenergy-efficient way unlike traditional hardware approaches. To this end, wehave endeavored to design and implement compiler-directed soft error resiliencetechniques.
When physicists developed sensor based soft error detection, computer architectstook it as a key technol- ogy for SDC-freedom due to the ability to senseparticle strikes and proposed a coarse-grained hardware checkpointing forrecovery. However, since not all the strikes lead to soft errors, we believedthat a fine- grained recovery such as idempotent processing must be used totolerate the false positives. In fact, it was an open problem how to combinesensor-based detection and idempotence-based recovery with no detecteduncorrectable error (DUE). The crux of the problem is that the detection latency(sensing time) makes it pos- sible for soft errors to escape the idempotentregion where they occur. To prevent such DUEs by ensuring region-level errorcontainment, we created tail-DMR, a selective instruction duplication scheme.The compiler identifies the DUE-vulnerable instructions at the tail of eachidempotent region and duplicates them for in- stant error detection so thattheir errors are contained in the region. This research lays the groundwork forother compiler-directed error resilience schemes.
Later, we found out that the region-level error containment can be obviated byredefining the idempotent processing from the processor’s point of view tocontain the errors within the core. The key idea is to regard the committedstores of each region as unverified, holding them in a gated store queue (GSQ)until they become error-free, i.e., no sensor raises the alarm during thedetection latency period after the boundary (end) of the region; a new logiccalled region boundary buffer (RBB) precisely gates/releases the GSQ by trackingthe end time of regions. That way the processor core never merges unverifiedstores to cache, and the recovery can be made by flushing the GSQ on error andrestarting from the most recently verified region boundary. That is, theregion-level error containment is relaxed to core-level containment! The upshotis that it requires neither extra error detection such as the tail-DMR norcomplex hardware modification as in prior work that replicatesmicroarchitectural components and modifies cache coherence protocols. Thisresearch has inspired the design and use of the GSQ-driven recovery fordifferent problem domains such as nonvolatile processors used in energyharvesting systems.
The irony of the original idempotent processing is that although it is to beused for lightweight soft error recovery, it requires expensive hardware support(e.g., 100% soft-error tolerant register file) and incurs significant executiontime overhead. Considering that soft errors rarely occur (e.g., ≈ one per day),no one would be willing to adopt the idempotent processing for such rare errorcorrection at the cost of paying the significant performance overhead all day.To this end, we developed two effective compiler optimization techniques, i.e.,eager checkpointing and checkpoint pruning. To remove the need of the expensivehardware support, the compiler protects the register inputs of each idempotentregion during their entire liveness period by eagerly checkpointing the inputvalues right after they are defined.  To minimize the checkpoint overhead, wecreated a novel program analysis that identifies and eliminates thosecheckpoints whose value can be safely reconstructed by other values of existingcheckpoints. The beauty of this approach is that it shifts the runtime overheadof the soft-error free execution to that of the error recovery execution withoutcompromising the recovery guarantee, thereby promoting the wide use ofidempotent processing!