Intellectual Merit:

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the presence of large manufacturing process variations. A high-resolution Trojan detection method for digital logic based on pulse propagation was developed. The method exhibits 25X – 30X higher diagnostic resolution (ability to measure small capacitive loads on internal circuit nodes) as compared to current path delay based Trojan detection techniques in the presence of significant manufacturing process variations. Further, a key benefit is that theoretically, as opposed to path delay measurement based methods, the diagnostic resolution of the test approach is independent of circuit logic depth over and above the benefits already mentioned above. Test methods and test infrastructure compatible with existing scan based techniques are described. Simulation results are presented to prove the viability and effectiveness of the proposed Trojan detection scheme and especially for circuits with large logic depths (35-70 gates) suffering from worst case process variation effects.

The above pulse propagation based Trojan detection is independent of logic depth in the path. As the logic depth increases however, the  Trojan detection scheme  loses some accuracy. Though the scheme appears simple, it is not so straight forward to generate and apply the pulse inputs on chip at the desired locations and capture them at designated locations with high accuracy in presence of high fan out nodes in the design. Aa very high resolution current sensing scheme to detect pulse propagation through logic gates was developed. A single sensor can sense pulse at multiple locations. The entire scheme of pulse based Trojan detection has been integrated into JTAG boundary scan scheme with minimal area overhead to provide a complete solution for detection of hardware Trojans.

With regard to mixed-signal, the test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and allow test generation to scale to different applications, we propose a new approach in which FSM models of mixed-signal/RF circuits are abstracted from hardware measurements on fabricated devices. These models allow accurate simulation of device behavior under arbitrary stimulus and thereby test stimulus generation, even after the device has been shipped to a customer. As a consequence, it becomes possible to detect process shifts with fine granularity and regenerate tests to adapt to process perturbations in a dynamic manner without losing test accuracy. A complete methodology for such adaptive testing of mixed-signal/RF circuits for manufacturing defect and design bug (Trojan) detection was developed.. Simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

A test generation algorithm that concurrently tests for the smallest possible (maliciously inserted) capacitive loading of internal nodes of mixed-signal/RF circuits has been developed at Georgia Tech  and is the first test generation of  its kind. 

Broader Impact:

There were several interactions with SRC member companies with presentations made to industry representatives from US semiconductor companies (6 workshops/review meetings overall, one in the US and one in Bangalore, India per year). These resulted in interesting discussions and perspectives from industry. Each review was followed up by a research evaluation that was necessary for continued SRC support. All the reviews were positive and successful.  One of the graduate students working on the project has graduated and joined Intel Corporation, Another student is expected to graduate in May 2018 and has already been in contact with US industry.  The work also led to collaborative discussions with Prof. A. D. Singh of Auburn University and Prof. Ilia Polian of the University of Stuttgart, Germany (Prof. Singh is a co-author on one of the papers published through this research). There is potential to pushing the results of this research to other domains such as public PUFs. Some of the work received help from UC Berkeley as well with research interactions between Prof. Chatterjee’s group and Prof. J. Rowchowdhury’s group at UC Berkeley).

Besides the research interactions ad technology transfer, significant infrastructure has been developed at Georgia Tech that future students can leverage. This includes a test generation system that generates tests from stimulation of hardware. This is a capability that does  not exist elsewhere and has been developed at Georgia Tech. Prof. Chatterjee has also participated in H.O.T days at Georgia Tech, a summer program designed to encourage high school students to pursue engineering as a career path.

Last Modified: 12/28/2017
Modified by: Abhijit Chatterjee