Award Abstract # 0811781
Collaborative Research: CPA-CPL-T: An Effective Automatic Parallelization Framework for Multi-Core Architectures

NSF Org: CCF
Division of Computing and Communication Foundations
Recipient:
Initial Amendment Date: July 22, 2008
Latest Amendment Date: June 2, 2009
Award Number: 0811781
Award Instrument: Standard Grant
Program Manager: Almadena Chtchelkanova
achtchel@nsf.gov
 (703)292-7498
CCF
 Division of Computing and Communication Foundations
CSE
 Directorate for Computer and Information Science and Engineering
Start Date: August 1, 2008
End Date: July 31, 2012 (Estimated)
Total Intended Award Amount: $500,000.00
Total Awarded Amount to Date: $516,000.00
Funds Obligated to Date: FY 2008 = $500,000.00
FY 2009 = $16,000.00
History of Investigator:
  • Ponnuswamy Sadayappan (Principal Investigator)
    saday@cs.utah.edu
  • Atanas Rountev (Co-Principal Investigator)
Recipient Sponsored Research Office: Ohio State University Research Foundation -DO NOT USE
1960 KENNY RD
Columbus
OH  US  43210-1016
(614)688-8734
Sponsor Congressional District: 03
Primary Place of Performance: Ohio State University
1960 KENNY RD
COLUMBUS
OH  US  43210-1016
Primary Place of Performance
Congressional District:
03
Unique Entity Identifier (UEI): QR7NH79713E5
Parent UEI:
NSF Program(s): COMPILERS,
Software & Hardware Foundation
Primary Program Source: 01000809DB NSF RESEARCH & RELATED ACTIVIT
01000910DB NSF RESEARCH & RELATED ACTIVIT
Program Reference Code(s): 9218, 9251, HPCC
Program Element Code(s): 732900, 779800
Award Agency Code: 4900
Fund Agency Code: 4900
Assistance Listing Number(s): 47.070

ABSTRACT

The ubiquity of multi-core processors has brought parallel computing squarely into the mainstream. It is now essential to develop parallel implementations of a large number of existing sequential codes. The difficulty of programming these architectures to effectively tap the potential of multiple on-chip processing units is a significant challenge. Although there has been significant progress in compiler techniques towards automatic parallelization, the current state-of-practice leaves much to be desired. The pressing need for systematic, general, and effective theoretical foundations for such efforts is a major motivation for this project.

This project will build on some very recent developments using polyhedral models showing great promise for developing effective automatic parallelization frameworks for multi-core architectures.
With the polyhedral model, it is possible to reason about the correctness of complex loop transformations in a completely mathematical setting using powerful machinery from linear algebra and linear programming. This enables effective integrated transformation, and therefore can be the basis for developing a very powerful automatic parallelization framework that can target different multi-core platforms. The project will address a number of key issues that are very important in developing an automatic parallelization and data locality optimization framework that is effective over a range of user application codes: (i) model-driven search for determination of effective tile sizes and loop fusion choices; (ii) extended tiling approaches like overlapped/split tiles to enhance concurrency; (iii) automatic generation of parallel code for accelerators with multiple distinct address spaces; and (iv) development of an extensive benchmark suite for assessment of automatic parallelization systems.
The developed software will be made publicly available.

PUBLICATIONS PRODUCED AS A RESULT OF THIS RESEARCH

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(Showing: 1 - 10 of 14)
A. Hartono, M. Baskaran, C. Bastoul, A. Cohen, S. Krishnamoorthy, B. Norris, J. Ramanujam, and P. Sadayappan "Parametric Multi-Level Tiling of Imperfectly Nested Loops" International Conference on Supercomputing (ICS) , 2009
Albert Hartono, Muthu Manikandan Baskaran, J. Ramanujam, and P. Sadayappan "DynTile: Parametric Tiled Loop Generation for Effective Parallel Execution on Multicore Processors" IEEE International Parallel and Distributed Processing Symposium (IPDPS) , 2010
Atanas Rountev, Kevin Van Valkenburgh, Dacong Yan, and P. Sadayappan "Understanding Parallelism-Inhibiting Dependences in Sequential Java Programs" IEEE International Conference on Software Maintenance (ICSM) , 2010
Jun Shirako, Kamal Sharma, Naznin Fauzia, Louis-Noel Pouchet, J. Ramanujam, P. Sadayappan, and Vivek Sarkar "Analytical Bounds for Optimal Tile Size Selection" International Conference on Compiler Construction (CC) , 2012
Justin Holewinski, Louis-Noel Pouchet, and P. Sadayappan "High-Performance Code Generation for Stencil Computations on GPU Architectures" ACM International Conference on Supercomputing (ICS) , 2012
Justin Holewinski, Ragavendar Ramamurthi, Mahesh Ravishankar, Naznin Fauzia, Louis-Noel Pouchet, Atanas Rountev, and P. Sadayappan "Dynamic Trace-Based Analysis of Vectorization Potential of Applications" ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) , 2012
Kevin Stock, Louis-Noel Pouchet, and P. Sadayappan "Using Machine Learning to Improve Automatic Vectorization" ACM Transactions on Architecture and Code Optimization (TACO) , v.8 , 2012
Kevin Stock, Tom Henretty, Iyyappa Murugandi, P. Sadayappan, and Robert Harrison "Model-Driven SIMD Code Generation for a Multi-Resolution Tensor Kernel" IEEE International Parallel and Distributed Processing Symposium (IPDPS) , 2011
Louis-Noel Pouchet, Uday Bondhugula, Cedric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, and Nicolas Vasilache "Loop Transformations: Convexity, Pruning and Optimization" ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages (POPL) , 2011
Muthu Baskaran, J. Ramanujam, and P. Sadayappan "Automatic C-to-CUDA Code Generation for Affine Programs" International Conference on Compiler Construction (CC) , 2010
Muthu Baskaran, Nagavijayalakshmi Vydyanathan, Uday Bondhugula, J. Ramanujam, Atanas Rountev, and P. Sadayappan "Compiler-Assisted Dynamic Scheduling for Effective Parallelization of Loop Nests on Multicore Processors" ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) , 2009
(Showing: 1 - 10 of 14)

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